From ca2b3feed82f923f06d0cf57787818f0f6793157 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 1 Mar 2019 19:25:23 +0100 Subject: [PATCH 01/12] Fix ECP5 cells_sim for iverilog --- techlibs/ecp5/cells_sim.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v index 8320ee70a..1e4002ee0 100644 --- a/techlibs/ecp5/cells_sim.v +++ b/techlibs/ecp5/cells_sim.v @@ -223,11 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q); wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; + wire srval; generate if (LSRMODE == "PRLD") - wire srval = M; + assign srval = M; else - localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0; + assign srval = (REGSET == "SET") ? 1'b1 : 1'b0; endgenerate initial Q = srval; From 03237de68605bb6eae73b96379faab0af6f8ce73 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Mar 2019 12:59:07 -0800 Subject: [PATCH 02/12] Fix "write_edif -gndvccy" Signed-off-by: Clifford Wolf --- backends/edif/edif.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 2d25f879d..7e30b67af 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -130,7 +130,7 @@ struct EdifBackend : public Backend { bool port_rename = false; bool attr_properties = false; std::map> lib_cell_ports; - bool nogndvcc = false, gndvccy = true; + bool nogndvcc = false, gndvccy = false; CellTypes ct(design); EdifNames edif_names; From 7cfae2c52fb8e210a68032a109646785e4353dcc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Mar 2019 13:35:09 -0800 Subject: [PATCH 03/12] Use mem2reg on memories that only have constant-index write ports Signed-off-by: Clifford Wolf --- frontends/ast/ast.h | 2 ++ frontends/ast/simplify.cc | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 08f91c9c3..89f7e6e4f 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -214,6 +214,8 @@ namespace AST MEM2REG_FL_SET_ASYNC = 0x00000800, MEM2REG_FL_EQ2 = 0x00001000, MEM2REG_FL_CMPLX_LHS = 0x00002000, + MEM2REG_FL_CONST_LHS = 0x00004000, + MEM2REG_FL_VAR_LHS = 0x00008000, /* proc flags */ MEM2REG_FL_EQ1 = 0x01000000, diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 46013544b..589c683f8 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -113,6 +113,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (memflags & AstNode::MEM2REG_FL_CMPLX_LHS) goto verbose_activate; + if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS)) + goto verbose_activate; + // log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags)); continue; @@ -2936,6 +2939,14 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1; } + // remember if this is a constant index or not + if (children[0]->children.size() && children[0]->children[0]->type == AST_RANGE && children[0]->children[0]->children.size()) { + if (children[0]->children[0]->children[0]->type == AST_CONSTANT) + mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CONST_LHS; + else + mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_VAR_LHS; + } + // remember where this is if (flags & MEM2REG_FL_INIT) { if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT)) From a02d61576ec42931ed3a67c6900bcd5aeddaf8b8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 1 Mar 2019 14:29:17 -0800 Subject: [PATCH 04/12] Minor improvements in README Signed-off-by: Clifford Wolf --- README.md | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 883f2b0a5..f17046488 100644 --- a/README.md +++ b/README.md @@ -34,11 +34,24 @@ compatible license that is similar in terms to the MIT license or the 2-clause BSD license). -Web Site -======== +Web Site and Other Resources +============================ More information and documentation can be found on the Yosys web site: -http://www.clifford.at/yosys/ +- http://www.clifford.at/yosys/ + +The "Documentation" page on the web site contains links to more resources, +including a manual that even describes some of the Yosys internals: +- http://www.clifford.at/yosys/documentation.html + +The file `CodingReadme` in this directory contains additional information +for people interested in using the Yosys C++ APIs. + +Users interested in formal verification might want to use the formal verification +front-end for Yosys, SymbiYosys: +- https://symbiyosys.readthedocs.io/en/latest/ +- https://github.com/YosysHQ/SymbiYosys + Setup ====== From 57f8bb471feecafad9d9e0bae77ea937b6b03a83 Mon Sep 17 00:00:00 2001 From: Larry Doolittle Date: Fri, 1 Mar 2019 20:15:20 -0800 Subject: [PATCH 05/12] Try again for passes/pmgen/ice40_dsp_pm.h rule Tested on both in-tree and out-of-tree builds --- passes/pmgen/Makefile.inc | 2 +- passes/pmgen/pmgen.py | 15 ++++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index e0dd0fc06..e0609d9ba 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -5,4 +5,4 @@ EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h .SECONDARY: passes/pmgen/ice40_dsp_pm.h passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg - $(P) mkdir -p passes/pmgen && python3 $^ + $(P) mkdir -p passes/pmgen && python3 $^ $@ diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 762d8621f..d9747b065 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -9,7 +9,8 @@ pp = pprint.PrettyPrinter(indent=4) pmgfile = sys.argv[1] assert pmgfile.endswith(".pmg") prefix = pmgfile[0:-4] -pmname = prefix.split('/')[-1] +prefix = prefix.split('/')[-1] +outfile = sys.argv[2] state_types = dict() udata_types = dict() @@ -179,7 +180,7 @@ with open(pmgfile, "r") as f: blocks.append(block) -with open("%s_pm.h" % prefix, "w") as f: +with open(outfile, "w") as f: print("// Generated by pmgen.py from {}.pgm".format(prefix), file=f) print("", file=f) @@ -190,10 +191,10 @@ with open("%s_pm.h" % prefix, "w") as f: print("YOSYS_NAMESPACE_BEGIN", file=f) print("", file=f) - print("struct {}_pm {{".format(pmname), file=f) + print("struct {}_pm {{".format(prefix), file=f) print(" Module *module;", file=f) print(" SigMap sigmap;", file=f) - print(" std::function on_accept;".format(pmname), file=f) + print(" std::function on_accept;".format(prefix), file=f) print("", file=f) for index in range(len(blocks)): @@ -291,7 +292,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print(" {}_pm(Module *module, const vector &cells) :".format(pmname), file=f) + print(" {}_pm(Module *module, const vector &cells) :".format(prefix), file=f) print(" module(module), sigmap(module) {", file=f) for s, t in sorted(udata_types.items()): if t.endswith("*"): @@ -321,7 +322,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print(" ~{}_pm() {{".format(pmname), file=f) + print(" ~{}_pm() {{".format(prefix), file=f) print(" for (auto cell : autoremove_cells)", file=f) print(" module->remove(cell);", file=f) print(" }", file=f) @@ -340,7 +341,7 @@ with open("%s_pm.h" % prefix, "w") as f: print(" }", file=f) print("", file=f) - print(" void run(std::function on_accept_f) {{".format(pmname), file=f) + print(" void run(std::function on_accept_f) {{".format(prefix), file=f) print(" run([&](){on_accept_f(*this);});", file=f) print(" }", file=f) print("", file=f) From f75aee87e3038f663dc61f9d3098d5056ccdced7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Mar 2019 08:29:28 -0800 Subject: [PATCH 06/12] Disable macOS builds in Travis Signed-off-by: Clifford Wolf --- .travis.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.travis.yml b/.travis.yml index 8aacbb8b1..7c6e4e43c 100644 --- a/.travis.yml +++ b/.travis.yml @@ -132,11 +132,11 @@ matrix: env: - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0" - # Latest clang on Mac OS X - - os: osx - osx_image: xcode9.4 - env: - - MATRIX_EVAL="CONFIG=clang && CC=clang && CXX=clang++" +# # Latest clang on Mac OS X +# - os: osx +# osx_image: xcode9.4 +# env: +# - MATRIX_EVAL="CONFIG=clang && CC=clang && CXX=clang++" before_install: - ./.travis/setup.sh From 5d93dcce862d281f0df495eeee755cd4bfca342d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Mar 2019 09:58:20 -0800 Subject: [PATCH 07/12] Fix $readmem[hb] for mem2reg memories, fixes #785 Signed-off-by: Clifford Wolf --- frontends/ast/simplify.cc | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 589c683f8..1c35516d4 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -2172,6 +2172,8 @@ skip_dynamic_range_lvalue_expansion:; } newNode = readmem(str == "\\$readmemh", node_filename->bitsAsConst().decode_string(), node_memory->id2ast, start_addr, finish_addr, unconditional_init); + delete node_filename; + delete node_memory; goto apply_newNode; } @@ -3059,6 +3061,39 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, if (type == AST_FUNCTION || type == AST_TASK) return false; + if (type == AST_MEMINIT && id2ast && mem2reg_set.count(id2ast)) + { + log_assert(children[0]->type == AST_CONSTANT); + log_assert(children[1]->type == AST_CONSTANT); + log_assert(children[2]->type == AST_CONSTANT); + + int cursor = children[0]->asInt(false); + Const data = children[1]->bitsAsConst(); + int length = children[2]->asInt(false); + + if (length != 0) + { + AstNode *block = new AstNode(AST_INITIAL, new AstNode(AST_BLOCK)); + mod->children.push_back(block); + block = block->children[0]; + + int wordsz = GetSize(data) / length; + + for (int i = 0; i < length; i++) { + block->children.push_back(new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER, new AstNode(AST_RANGE, AstNode::mkconst_int(cursor+i, false))), mkconst_bits(data.extract(i*wordsz, wordsz).bits, false))); + block->children.back()->children[0]->str = str; + block->children.back()->children[0]->id2ast = id2ast; + block->children.back()->children[0]->was_checked = true; + } + } + + AstNode *newNode = new AstNode(AST_NONE); + newNode->cloneInto(this); + delete newNode; + + did_something = true; + } + if (type == AST_ASSIGN && block == NULL && children[0]->mem2reg_check(mem2reg_set)) { if (async_block == NULL) { From ce6695e22c7d2b8856ec5bb93a94264555aa55b5 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Mar 2019 10:38:13 -0800 Subject: [PATCH 08/12] Fix $global_clock handling vs autowire Signed-off-by: Clifford Wolf --- frontends/ast/simplify.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 1c35516d4..d0b31078a 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -941,7 +941,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } } if (current_scope.count(str) == 0) { - if (flag_autowire) { + if (flag_autowire || str == "\\$global_clock") { AstNode *auto_wire = new AstNode(AST_AUTOWIRE); auto_wire->str = str; current_ast_mod->children.push_back(auto_wire); From 3a51714451dbd5a0aec5d5167429f899950f2c4e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Mar 2019 11:40:57 -0800 Subject: [PATCH 09/12] Fix error for wire decl in always block, fixes #763 Signed-off-by: Clifford Wolf --- frontends/ast/genrtlil.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 2d591b29d..13383845a 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -544,7 +544,11 @@ struct AST_INTERNAL::ProcessGenerator break; case AST_WIRE: - log_file_error(ast->filename, ast->linenum, "Found wire declaration in block without label!\n"); + log_file_error(ast->filename, ast->linenum, "Found reg declaration in block without label!\n"); + break; + + case AST_ASSIGN: + log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n"); break; case AST_PARAMETER: From ae9286386de117991f887f919f5af3fac40173cc Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sat, 2 Mar 2019 12:36:46 -0800 Subject: [PATCH 10/12] Only run derive on blackbox modules when ports have dynamic size Signed-off-by: Clifford Wolf --- README.md | 3 +++ frontends/ast/ast.h | 1 + frontends/ast/simplify.cc | 19 +++++++++++++++++++ passes/hierarchy/hierarchy.cc | 2 +- 4 files changed, 24 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index f17046488..9bac468a7 100644 --- a/README.md +++ b/README.md @@ -309,6 +309,9 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The Verilog backend also does not output blackbox modules on default. +- The ``dynports'' attribute is used by the Verilog front-end to mark modules + that have ports with a width that depends on a parameter. + - The ``keep`` attribute on cells and wires is used to mark objects that should never be removed by the optimizer. This is used for example for cells that have hidden connections that are not part of the netlist, such as IO pads. diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 89f7e6e4f..8b185ff51 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -239,6 +239,7 @@ namespace AST bool has_const_only_constructs(bool &recommend_const_eval); void replace_variables(std::map &variables, AstNode *fcall); AstNode *eval_const_function(AstNode *fcall); + bool is_simple_const_expr(); // create a human-readable text representation of the AST (for debugging) void dumpAst(FILE *f, std::string indent) const; diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index d0b31078a..7160c6c0f 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -328,6 +328,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; if (node->type == AST_WIRE) { + if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { + for (auto c : node->children[0]->children) { + if (!c->is_simple_const_expr()) { + if (attributes.count("\\dynports")) + delete attributes.at("\\dynports"); + attributes["\\dynports"] = AstNode::mkconst_int(1, true); + } + } + } if (this_wire_scope.count(node->str) > 0) { AstNode *first_node = this_wire_scope[node->str]; if (first_node->is_input && node->is_reg) @@ -3323,6 +3332,16 @@ bool AstNode::has_const_only_constructs(bool &recommend_const_eval) return false; } +bool AstNode::is_simple_const_expr() +{ + if (type == AST_IDENTIFIER) + return false; + for (auto child : children) + if (!child->is_simple_const_expr()) + return false; + return true; +} + // helper function for AstNode::eval_const_function() void AstNode::replace_variables(std::map &variables, AstNode *fcall) { diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 2d8edebb5..88c339e8c 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -910,7 +910,7 @@ struct HierarchyPass : public Pass { if (m == nullptr) continue; - if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty()) { + if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { IdString new_m_name = m->derive(design, cell->parameters, true); if (new_m_name.empty()) continue; From a176ac95ded8b5aa9efb98b7a8e6981c90827d0e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Mar 2019 21:35:57 -0800 Subject: [PATCH 11/12] Update igloo2 example to Libero v12.0 Signed-off-by: Clifford Wolf --- examples/igloo2/libero.tcl | 9 ++++----- examples/igloo2/runme.sh | 2 +- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 1f3476316..82e614cd4 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -15,6 +15,7 @@ new_project \ import_files -hdl_source {netlist.vm} import_files -sdc {example.sdc} import_files -io_pdc {example.pdc} +build_design_hierarchy set_option -synth 0 organize_tool_files -tool PLACEROUTE \ @@ -44,10 +45,8 @@ puts "**> VERIFYTIMING" run_tool -name {VERIFYTIMING} puts "<** VERIFYTIMING" -save_project - -# puts "**> export_bitstream" -# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} -# puts "<** export_bitstream" +puts "**> export_bitstream" +export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} +puts "<** export_bitstream" exit 0 diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh index 54247759f..95f2282ba 100644 --- a/examples/igloo2/runme.sh +++ b/examples/igloo2/runme.sh @@ -1,4 +1,4 @@ #!/bin/bash set -ex yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v -LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl +LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl From 107d8848041289bdf3ed85f2ca6c7e02fa9ec774 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 3 Mar 2019 23:54:35 -0800 Subject: [PATCH 12/12] Improve igloo2 example Signed-off-by: Clifford Wolf --- examples/igloo2/libero.tcl | 9 +++++++-- examples/igloo2/runme.sh | 4 +++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index 82e614cd4..6f7d4e24b 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -33,20 +33,25 @@ configure_tool -name PLACEROUTE \ -params EFFORT_LEVEL:false \ -params REPAIR_MIN_DELAY:false +puts "" puts "**> COMPILE" run_tool -name {COMPILE} puts "<** COMPILE" +puts "" puts "**> PLACEROUTE" run_tool -name {PLACEROUTE} puts "<** PLACEROUTE" +puts "" puts "**> VERIFYTIMING" run_tool -name {VERIFYTIMING} puts "<** VERIFYTIMING" -puts "**> export_bitstream" +puts "" +puts "**> BITSTREAM" export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC} -puts "<** export_bitstream" +puts "<** BITSTREAM" +puts "" exit 0 diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh index 95f2282ba..a08894e0a 100644 --- a/examples/igloo2/runme.sh +++ b/examples/igloo2/runme.sh @@ -1,4 +1,6 @@ #!/bin/bash set -ex yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v -LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl +export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost} +/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl +cp proj/designer/example/export/example.stp .