riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added support for "always @(*)"

This commit is contained in:
Clifford Wolf 2013-01-16 17:32:11 +01:00
parent e8231ee46b
commit 6d1502b948
2 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -74,7 +74,7 @@ or using a simple synthesis script:
proc; opt; techmap; opt proc; opt; techmap; opt
write_verilog synth.v write_verilog synth.v
$ ././yosys synth.ys $ ./yosys synth.ys
It is also possible to only have the synthesis commands but not the read/write It is also possible to only have the synthesis commands but not the read/write
commands in the synthesis script: commands in the synthesis script:

3
frontends/verilog/parser.y
View File

@ -616,6 +616,9 @@ always_stmt:
always_cond: always_cond:
'@' '(' always_events ')' | '@' '(' always_events ')' |
'@' '(' '*' ')' |
'@' ATTR_BEGIN ')' |
'@' '(' ATTR_END |
'@' '*' | '@' '*' |
/* empty */; /* empty */;