diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index c32095927..c3b2a2f5e 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -433,10 +433,14 @@ struct VerificSvaImporter
 			return;
 		}
 
-		if (inst->Type() == PRIM_SVA_UNTIL || inst->Type() == PRIM_SVA_S_UNTIL ||
+		if (inst->Type() == PRIM_SVA_THROUGHOUT || inst->Type() == PRIM_SVA_UNTIL || inst->Type() == PRIM_SVA_S_UNTIL ||
 				inst->Type() == PRIM_SVA_UNTIL_WITH || inst->Type() == PRIM_SVA_S_UNTIL_WITH)
 		{
-			bool flag_with = inst->Type() == PRIM_SVA_UNTIL_WITH || inst->Type() == PRIM_SVA_S_UNTIL_WITH;
+			bool flag_with = inst->Type() == PRIM_SVA_THROUGHOUT || inst->Type() == PRIM_SVA_UNTIL_WITH || inst->Type() == PRIM_SVA_S_UNTIL_WITH;
+
+			if (get_ast_input1(inst) != nullptr)
+				log_error("Currently only simple expression properties are supported as first operand to SVA_UNTIL.\n");
+
 			SigBit expr = importer->net_map_at(inst->GetInput1());
 
 			if (flag_with)
diff --git a/tests/sva/sva_until.sv b/tests/sva/sva_throughout.sv
similarity index 88%
rename from tests/sva/sva_until.sv
rename to tests/sva/sva_throughout.sv
index a721e44b5..7e036a066 100644
--- a/tests/sva/sva_until.sv
+++ b/tests/sva/sva_throughout.sv
@@ -5,7 +5,7 @@ module top (
 	default clocking @(posedge clk); endclocking
 
 	assert property (
-		a |=> b until_with (c ##1 d)
+		a |=> b throughout (c ##1 d)
 	);
 
 `ifndef FAIL