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opt_expr: Remove -clkinv option, make it the default. 

Adds -noclkinv option just in case the old behavior was actually useful
to someone.
This commit is contained in:
Marcelina Kościelnicka 2020-07-24 13:08:54 +02:00
parent cf60699884
commit 6cd135a5eb
5 changed files with 17 additions and 18 deletions
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10
passes/opt/opt.cc
View File

@ -37,7 +37,7 @@ struct OptPass : public Pass {
log("a series of trivial optimizations and cleanups. This pass executes the other\n");
log("passes in the following order:\n");
log("\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n");
log(" opt_merge [-share_all] -nomux\n");
log("\n");
log(" do\n");
@ -47,13 +47,13 @@ struct OptPass : public Pass {
log(" opt_share (-full only)\n");
log(" opt_rmdff [-keepdc] [-sat] (except when called with -noff)\n");
log(" opt_clean [-purge]\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n");
log(" while <changed design>\n");
log("\n");
log("When called with -fast the following script is used instead:\n");
log("\n");
log(" do\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-clkinv] [-fine] [-full] [-keepdc]\n");
log(" opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]\n");
log(" opt_merge [-share_all]\n");
log(" opt_rmdff [-keepdc] [-sat] (except when called with -noff)\n");
log(" opt_clean [-purge]\n");
@ -96,8 +96,8 @@ struct OptPass : public Pass {
opt_expr_args += " -undriven";
continue;
}
if (args[argidx] == "-clkinv") {
opt_expr_args += " -clkinv";
if (args[argidx] == "-noclkinv") {
opt_expr_args += " -noclkinv";
continue;
}
if (args[argidx] == "-fine") {

18
passes/opt/opt_expr.cc
View File

@ -416,7 +416,7 @@ int get_onehot_bit_index(RTLIL::SigSpec signal)
return bit_index;
}
void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool clkinv)
void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv)
{
if (!design->selected(module))
return;
@ -465,7 +465,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
#define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))
if (clkinv)
if (!noclkinv)
{
if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memwr)))
handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
@ -2064,8 +2064,8 @@ struct OptExprPass : public Pass {
log(" -undriven\n");
log(" replace undriven nets with undef (x) constants\n");
log("\n");
log(" -clkinv\n");
log(" optimize clock inverters by changing FF types\n");
log(" -noclkinv\n");
log(" do not optimize clock inverters by changing FF types\n");
log("\n");
log(" -fine\n");
log(" perform fine-grain optimizations\n");
@ -2085,7 +2085,7 @@ struct OptExprPass : public Pass {
bool mux_undef = false;
bool mux_bool = false;
bool undriven = false;
bool clkinv = false;
bool noclkinv = false;
bool do_fine = false;
bool keepdc = false;
@ -2106,8 +2106,8 @@ struct OptExprPass : public Pass {
undriven = true;
continue;
}
if (args[argidx] == "-clkinv") {
clkinv = true;
if (args[argidx] == "-noclkinv") {
noclkinv = true;
continue;
}
if (args[argidx] == "-fine") {
@ -2144,12 +2144,12 @@ struct OptExprPass : public Pass {
do {
do {
did_something = false;
replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv);
replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
} while (did_something);
if (!keepdc)
replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, clkinv);
replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
} while (did_something);

2
techlibs/greenpak4/synth_greenpak4.cc
View File

@ -162,7 +162,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
run("opt -undriven -fine");
run("techmap -map +/techmap.v -map +/greenpak4/cells_latch.v");
run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
run("opt -fast");
run("opt -fast -noclkinv -noff");
if (retime || help_mode)
run("abc -dff -D 1", "(only if -retime)");
}

2
techlibs/xilinx/synth_xilinx.cc
View File

@ -585,7 +585,7 @@ struct SynthXilinxPass : public ScriptPass
}
if (check_label("map_luts")) {
run("opt_expr -mux_undef");
run("opt_expr -mux_undef -noclkinv");
if (flatten_before_abc)
run("flatten");
if (help_mode)

3
tests/arch/xilinx/latches.ys
View File

@ -18,9 +18,8 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad #
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
select -assert-count 1 t:INV
select -assert-none t:LDCE t:INV %% t:* %D
select -assert-none t:LDCE %% t:* %D
design -load read