riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Indent fix 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-06-05 09:53:06 +02:00
parent 00d32eb73d
commit 6cc60ffd67
1 changed files with 22 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
passes/cmds/setundef.cc
View File

@ -404,9 +404,11 @@ struct SetundefPass : public Pass {
initwires.insert(wire); initwires.insert(wire);
} }
for (int wire_types = 0; wire_types < 2; wire_types++) { for (int wire_types = 0; wire_types < 2; wire_types++)
{
pool<SigBit> ffbitsToErase; pool<SigBit> ffbitsToErase;
for (auto wire : module->wires()) { for (auto wire : module->wires())
{
if (wire->name[0] == (wire_types ? '\\' : '$')) { if (wire->name[0] == (wire_types ? '\\' : '$')) {
next_wire: next_wire:
continue; continue;
@ -423,7 +425,7 @@ struct SetundefPass : public Pass {
initwires.insert(wire); initwires.insert(wire);
} }
for (const auto &bit : ffbitsToErase) { for (const auto & bit : ffbitsToErase) {
ffbits.erase(bit); ffbits.erase(bit);
} }
} }