Fixed trailing whitespaces

README

@@ -63,7 +63,7 @@ There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
 as a source distribution for Visual Studio. Visit the Yosys download page for
 more information:
 
-	http://www.clifford.at/yosys/download.html 
+	http://www.clifford.at/yosys/download.html
 
 To configure the build system to use a specific compiler, use one of
 

backends/blif/blif.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

backends/btor/README

@@ -6,7 +6,7 @@ Master git repository for the BTOR backend:
 https://github.com/ahmedirfan1983/yosys
 
 
-[[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking 
+[[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking
 Johannes Kepler University, Linz, Austria
 http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf
 

backends/btor/btor.cc

@@ -3,11 +3,11 @@
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
  *  Copyright (C) 2014  Ahmed Irfan <irfan@fbk.eu>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -18,7 +18,7 @@
  *
  */
 
-// [[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking 
+// [[CITE]] BTOR: Bit-Precise Modelling of Word-Level Problems for Model Checking
 // Johannes Kepler University, Linz, Austria
 // http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf
 
@@ -75,10 +75,10 @@ struct BtorDumper
 	std::map<RTLIL::SigSpec, int> sig_ref;//mapping of sigspec to the line_num of the btor file
 	int line_num;//last line number of btor file
 	std::string str;//temp string for writing file
-	std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers	
+	std::map<RTLIL::IdString, bool> basic_wires;//input wires and registers
 	RTLIL::IdString curr_cell; //current cell being dumped
 	std::map<std::string, std::string> cell_type_translation, s_cell_type_translation; //RTLIL to BTOR translation
-        std::map<int, std::set<std::pair<int,int>>> mem_next; // memory (line_number)'s set of condition and write 
+        std::map<int, std::set<std::pair<int,int>>> mem_next; // memory (line_number)'s set of condition and write
     	BtorDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BtorDumperConfig *config) :
     		f(f), module(module), design(design), config(config), ct(design), sigmap(module)
 	{
@@ -143,7 +143,7 @@ struct BtorDumper
 		//concat
 		cell_type_translation["$concat"] = "concat";
 
-		//signed cell type translation 
+		//signed cell type translation
 		//binary
 		s_cell_type_translation["$modx"] = "srem";
 		s_cell_type_translation["$mody"] = "smod";
@@ -152,9 +152,9 @@ struct BtorDumper
 		s_cell_type_translation["$le"] = "slte";
 		s_cell_type_translation["$gt"] = "sgt";
 		s_cell_type_translation["$ge"] = "sgte";
-		 
+
 	}
-	
+
 	vector<shared_str> cstr_buf;
 
 	const char *cstr(const RTLIL::IdString id)
@@ -166,17 +166,17 @@ struct BtorDumper
 		cstr_buf.push_back(str);
 		return cstr_buf.back().c_str();
 	}
-	
+
 	int dump_wire(RTLIL::Wire* wire)
 	{
 		if(basic_wires[wire->name])
-		{	
+		{
 			log("writing wire %s\n", cstr(wire->name));
 			auto it = line_ref.find(wire->name);
 			if(it==std::end(line_ref))
 			{
 				++line_num;
-				line_ref[wire->name]=line_num;			
+				line_ref[wire->name]=line_num;
 				str = stringf("%d var %d %s", line_num, wire->width, cstr(wire->name));
 				f << stringf("%s\n", str.c_str());
 				return line_num;
@@ -200,7 +200,7 @@ struct BtorDumper
 					log(" -- found cell %s\n", cstr(cell_id));
 					RTLIL::Cell* cell = module->cells_.at(cell_id);
 					const RTLIL::SigSpec* cell_output = get_cell_output(cell);
-					int cell_line = dump_cell(cell);				
+					int cell_line = dump_cell(cell);
 
 					if(dep_set.size()==1 && wire->width == cell_output->size())
 					{
@@ -235,7 +235,7 @@ struct BtorDumper
 				}
 				if(dep_set.size()==0)
 				{
-					log(" - checking sigmap\n");						
+					log(" - checking sigmap\n");
 					RTLIL::SigSpec s = RTLIL::SigSpec(wire);
 					wire_line = dump_sigspec(&s, s.size());
 					line_ref[wire->name]=wire_line;
@@ -243,16 +243,16 @@ struct BtorDumper
 				line_ref[wire->name]=wire_line;
 				return wire_line;
 			}
-			else 
+			else
 			{
-				log(" -- already processed wire\n");			
+				log(" -- already processed wire\n");
 				return it->second;
 			}
 		}
 		log_abort();
 		return -1;
 	}
-	
+
 	int dump_memory(const RTLIL::Memory* memory)
 	{
 		log("writing memory %s\n", cstr(memory->name));
@@ -262,7 +262,7 @@ struct BtorDumper
 			++line_num;
 			int address_bits = ceil(log(memory->size)/log(2));
 			str = stringf("%d array %d %d", line_num, memory->width, address_bits);
-			line_ref[memory->name]=line_num;			
+			line_ref[memory->name]=line_num;
 			f << stringf("%s\n", str.c_str());
 			return line_num;
 		}
@@ -300,7 +300,7 @@ struct BtorDumper
 		      f << stringf("%s\n", str.c_str());
 		    }
 		  ++line_num;
-		  str = stringf("%d anext %d %d %d %d", line_num, memory->width, address_bits, mem_it->second, line_num-1);                                                                                                                 
+		  str = stringf("%d anext %d %d %d %d", line_num, memory->width, address_bits, mem_it->second, line_num-1);
 		  f << stringf("%s\n", str.c_str());
 		  return 1;
 		}
@@ -326,11 +326,11 @@ struct BtorDumper
 			return line_num;
 		}
 		else
-			log("writing const error\n");		
+			log("writing const error\n");
 		log_abort();
 		return -1;
 	}
-	
+
 	int dump_sigchunk(const RTLIL::SigChunk* chunk)
 	{
 		log("writing sigchunk\n");
@@ -338,21 +338,21 @@ struct BtorDumper
 		if(chunk->wire == NULL)
 		{
 			RTLIL::Const data_const(chunk->data);
-			l=dump_const(&data_const, chunk->width, chunk->offset);			
+			l=dump_const(&data_const, chunk->width, chunk->offset);
 		}
 		else
 		{
 			if (chunk->width == chunk->wire->width && chunk->offset == 0)
 				l = dump_wire(chunk->wire);
-			else 
+			else
 			{
 				int wire_line_num = dump_wire(chunk->wire);
 				log_assert(wire_line_num>0);
 				++line_num;
-				str = stringf("%d slice %d %d %d %d;2", line_num, chunk->width, wire_line_num, 
+				str = stringf("%d slice %d %d %d %d;2", line_num, chunk->width, wire_line_num,
 					chunk->width + chunk->offset - 1, chunk->offset);
 				f << stringf("%s\n", str.c_str());
-				l = line_num;				 
+				l = line_num;
 			}
 		}
 		return l;
@@ -369,8 +369,8 @@ struct BtorDumper
 			if (s.is_chunk())
 			{
 				l = dump_sigchunk(&s.chunks().front());
-			} 
+			}
-			else 
+			else
 			{
 				int l1, l2, w1, w2;
 				l1 = dump_sigchunk(&s.chunks().front());
@@ -395,7 +395,7 @@ struct BtorDumper
 		{
 			l = it->second;
 		}
-		
+
 		if (expected_width != s.size())
 		{
 			log(" - changing width of sigspec\n");
@@ -422,7 +422,7 @@ struct BtorDumper
 		log_assert(l>0);
 		return l;
 	}
-	
+
 	int dump_cell(const RTLIL::Cell* cell)
 	{
 		auto it = line_ref.find(cell->name);
@@ -466,10 +466,10 @@ struct BtorDumper
 				int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				w = w>output_width ? w:output_width; //padding of w
-				int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w);				
+				int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w);
 				int cell_line = l;
 				if(cell->type != "$pos")
-				{	
+				{
 					cell_line = ++line_num;
 					bool reduced = (cell->type == "$not" || cell->type == "$neg") ? false : true;
 					str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type.str()).c_str(), reduced?output_width:w, l);
@@ -481,7 +481,7 @@ struct BtorDumper
 					str = stringf ("%d slice %d %d %d %d;4", line_num, output_width, cell_line, output_width-1, 0);
 					f << stringf("%s\n", str.c_str());
 					cell_line = line_num;
-				}				
+				}
 				line_ref[cell->name]=cell_line;
 			}
 			else if(cell->type == "$reduce_xnor" || cell->type == "$logic_not")//no direct translation in btor
@@ -502,7 +502,7 @@ struct BtorDumper
 					++line_num;
 					str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$reduce_xor").c_str(), output_width, l);
 					f << stringf("%s\n", str.c_str());
-				}		
+				}
 				++line_num;
 				str = stringf ("%d %s %d %d", line_num, cell_type_translation.at("$not").c_str(), output_width, l);
 				f << stringf("%s\n", str.c_str());
@@ -510,7 +510,7 @@ struct BtorDumper
 			}
 			//binary cells
 			else if(cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" ||
-				 cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" || 
+				 cell->type == "$lt" || cell->type == "$le" || cell->type == "$eq" || cell->type == "$ne" ||
 				 cell->type == "$eqx" || cell->type == "$nex" || cell->type == "$ge" || cell->type == "$gt" )
 			{
 				log("writing binary cell - %s\n", cstr(cell->type));
@@ -521,15 +521,15 @@ struct BtorDumper
 				bool l2_signed YS_ATTRIBUTE(unused) = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
-				
+
 				log_assert(l1_signed == l2_signed);
-				l1_width = l1_width > output_width ? l1_width : output_width;					
+				l1_width = l1_width > output_width ? l1_width : output_width;
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
 				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
-				
+
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type.str());
 				if(cell->type == "$lt" || cell->type == "$le" ||
@@ -539,13 +539,13 @@ struct BtorDumper
 					if(l1_signed)
 						op = s_cell_type_translation.at(cell->type.str());
 				}
-				
+
 				str = stringf ("%d %s %d %d %d", line_num, op.c_str(), output_width, l1, l2);
 				f << stringf("%s\n", str.c_str());
 
 				line_ref[cell->name]=line_num;
 			}
-			else if(cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" || 
+			else if(cell->type == "$add" || cell->type == "$sub" || cell->type == "$mul" || cell->type == "$div" ||
 				 cell->type == "$mod" )
 			{
 				//TODO: division by zero case
@@ -555,15 +555,15 @@ struct BtorDumper
 				bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
 				int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
 				int l2_width = 	cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
-				
+
 				log_assert(l1_signed == l2_signed);
-				l1_width = l1_width > output_width ? l1_width : output_width;					
+				l1_width = l1_width > output_width ? l1_width : output_width;
 				l1_width = l1_width > l2_width ? l1_width : l2_width;
 				l2_width = l2_width > l1_width ? l2_width : l1_width;
 
 				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
-				
+
 				++line_num;
 				std::string op = cell_type_translation.at(cell->type.str());
 				if(cell->type == "$div" && l1_signed)
@@ -631,7 +631,7 @@ struct BtorDumper
 					f << stringf("%s\n", str.c_str());
 					cell_output = line_num;
 				}
-				line_ref[cell->name] = cell_output;	
+				line_ref[cell->name] = cell_output;
 			}
 			else if(cell->type == "$logic_and" || cell->type == "$logic_or")//no direct translation in btor
 			{
@@ -678,7 +678,7 @@ struct BtorDumper
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width);
 				int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1);
 				++line_num;
-				str = stringf ("%d %s %d %d %d %d", 
+				str = stringf ("%d %s %d %d %d %d",
 					line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, s, l2, l1);
 				//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
 				f << stringf("%s\n", str.c_str());
@@ -693,7 +693,7 @@ struct BtorDumper
                           int cases = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width*select_width);
                           int select = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), select_width);
                           int *c = new int[select_width];
-                          
+
                           for (int i=0; i<select_width; ++i)
                           {
                             ++line_num;
@@ -701,15 +701,15 @@ struct BtorDumper
                             f << stringf("%s\n", str.c_str());
                             c[i] = line_num;
                             ++line_num;
-                            str = stringf ("%d slice %d %d %d %d", line_num, output_width, cases, i*output_width+output_width-1, 
+                            str = stringf ("%d slice %d %d %d %d", line_num, output_width, cases, i*output_width+output_width-1,
                                            i*output_width);
                             f << stringf("%s\n", str.c_str());
                           }
-                          
+
                           ++line_num;
                           str = stringf ("%d cond %d %d %d %d", line_num, output_width, c[select_width-1], c[select_width-1]+1, default_case);
                           f << stringf("%s\n", str.c_str());
-                          
+
                           for (int i=select_width-2; i>=0; --i)
                           {
                             ++line_num;
@@ -741,7 +741,7 @@ struct BtorDumper
 					{
 						start_bit+=output_width;
 						slice = ++line_num;
-						str = stringf ("%d slice %d %d %d %d;", line_num, output_width, value, start_bit-1, 
+						str = stringf ("%d slice %d %d %d %d;", line_num, output_width, value, start_bit-1,
 							start_bit-output_width);
 						f << stringf("%s\n", str.c_str());
 					}
@@ -753,16 +753,16 @@ struct BtorDumper
 							output_width);
 						bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
 						++line_num;
-						str = stringf ("%d %s %d %s%d %s%d %d", line_num, cell_type_translation.at("$mux").c_str(), 
+						str = stringf ("%d %s %d %s%d %s%d %d", line_num, cell_type_translation.at("$mux").c_str(),
-							output_width, sync_reset_pol ? "":"-", sync_reset, sync_reset_value_pol? "":"-", 
+							output_width, sync_reset_pol ? "":"-", sync_reset, sync_reset_value_pol? "":"-",
 							sync_reset_value, slice);
 						f << stringf("%s\n", str.c_str());
 						slice = line_num;
 					}
 					++line_num;
-					str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(), 
+					str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(),
 						output_width, polarity?"":"-", cond, slice, reg);
-				
+
 					f << stringf("%s\n", str.c_str());
 					int next = line_num;
 					if(cell->type == "$adff")
@@ -772,12 +772,12 @@ struct BtorDumper
 						int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
 							output_width, 0);
 						++line_num;
-						str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(), 
+						str = stringf ("%d %s %d %s%d %d %d", line_num, cell_type_translation.at("$mux").c_str(),
 							output_width, async_reset_pol ? "":"-", async_reset, async_reset_value, next);
 						f << stringf("%s\n", str.c_str());
 					}
 					++line_num;
-					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), 
+					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(),
 						output_width, reg, next);
 					f << stringf("%s\n", str.c_str());
 				}
@@ -795,7 +795,7 @@ struct BtorDumper
 				int address = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ADDR")), address_width);
 				int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
 				++line_num;
-				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);	
+				str = stringf("%d read %d %d %d", line_num, data_width, mem, address);
 				f << stringf("%s\n", str.c_str());
 				line_ref[cell->name]=line_num;
 			}
@@ -829,7 +829,7 @@ struct BtorDumper
                                         f << stringf("%s\n", str.c_str());
                                         mem = line_num - 1;
 				}
-				*/			       
+				*/
                 		++line_num;
 				if(polarity)
 					str = stringf("%d one 1", line_num);
@@ -837,21 +837,21 @@ struct BtorDumper
 					str = stringf("%d zero 1", line_num);
 				f << stringf("%s\n", str.c_str());
 				++line_num;
-				str = stringf("%d eq 1 %d %d", line_num, clk, line_num-1);	
+				str = stringf("%d eq 1 %d %d", line_num, clk, line_num-1);
 				f << stringf("%s\n", str.c_str());
 				++line_num;
-				str = stringf("%d and 1 %d %d", line_num, line_num-1, enable);	
+				str = stringf("%d and 1 %d %d", line_num, line_num-1, enable);
 				f << stringf("%s\n", str.c_str());
 				++line_num;
-				str = stringf("%d write %d %d %d %d %d", line_num, data_width, address_width, mem, address, data);	
+				str = stringf("%d write %d %d %d %d %d", line_num, data_width, address_width, mem, address, data);
 				f << stringf("%s\n", str.c_str());
 				/*
 				++line_num;
-				str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2, line_num-1, mem);	
+				str = stringf("%d acond %d %d %d %d %d", line_num, data_width, address_width, line_num-2, line_num-1, mem);
-				f << stringf("%s\n", str.c_str());				
+				f << stringf("%s\n", str.c_str());
 				++line_num;
-				str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1);	
+				str = stringf("%d anext %d %d %d %d", line_num, data_width, address_width, mem, line_num-1);
-				f << stringf("%s\n", str.c_str());				
+				f << stringf("%s\n", str.c_str());
 				*/
 				mem_next[mem].insert(std::make_pair(line_num-1, line_num));
 			}
@@ -865,11 +865,11 @@ struct BtorDumper
 				const RTLIL::SigSpec* output YS_ATTRIBUTE(unused) = &cell->getPort(RTLIL::IdString("\\Y"));
 				int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
 				log_assert(output->size() == output_width);
-				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
+				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();
 				++line_num;
 				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, input_line, output_width+offset-1, offset);
-				f << stringf("%s\n", str.c_str());				
+				f << stringf("%s\n", str.c_str());
-				line_ref[cell->name]=line_num;	
+				line_ref[cell->name]=line_num;
 			}
 			else if(cell->type == "$concat")
 			{
@@ -883,10 +883,10 @@ struct BtorDumper
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
 				++line_num;
-				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width, 
+				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width,
-					input_a_line, input_b_line);	
+					input_a_line, input_b_line);
-				f << stringf("%s\n", str.c_str());				
+				f << stringf("%s\n", str.c_str());
-				line_ref[cell->name]=line_num;				
+				line_ref[cell->name]=line_num;
 			}
 			curr_cell.clear();
 			return line_num;
@@ -912,7 +912,7 @@ struct BtorDumper
 		{
 			output_sig = &cell->getPort(RTLIL::IdString("\\Q"));
 		}
-		else 
+		else
 		{
 			output_sig = &cell->getPort(RTLIL::IdString("\\Y"));
 		}
@@ -930,7 +930,7 @@ struct BtorDumper
 	void dump()
 	{
 		f << stringf(";module %s\n", cstr(module->name));
-		
+
 		log("creating intermediate wires map\n");
 		//creating map of intermediate wires as output of some cell
 		for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it)
@@ -966,7 +966,7 @@ struct BtorDumper
 					basic_wires[wire_id] = true;
 				}
 			}
-			else 
+			else
 			{
 				for(unsigned i=0; i<output_sig->chunks().size(); ++i)
 				{
@@ -976,11 +976,11 @@ struct BtorDumper
 				}
 			}
 		}
-		
+
 		log("writing input\n");
 		std::map<int, RTLIL::Wire*> inputs, outputs;
 		std::vector<RTLIL::Wire*> safety;
-		
+
 		for (auto &wire_it : module->wires_) {
 			RTLIL::Wire *wire = wire_it.second;
 			if (wire->port_input)
@@ -998,7 +998,7 @@ struct BtorDumper
 			dump_wire(wire);
 		}
 		f << stringf("\n");
-		
+
 		log("writing memories\n");
 		for(auto mem_it = module->memories.begin(); mem_it != module->memories.end(); ++mem_it)
 		{
@@ -1014,9 +1014,9 @@ struct BtorDumper
 		log("writing cells\n");
 		for(auto cell_it = module->cells_.begin(); cell_it != module->cells_.end(); ++cell_it)
 		{
-			dump_cell(cell_it->second);	
+			dump_cell(cell_it->second);
 		}
-		
+
 		log("writing memory next");
 		for(auto mem_it = module->memories.begin(); mem_it != module->memories.end(); ++mem_it)
 		  {
@@ -1027,7 +1027,7 @@ struct BtorDumper
 			dump_property(it);
 
 		f << stringf("\n");
-		
+
 		log("writing outputs info\n");
 		f << stringf(";outputs\n");
 		for (auto &it : outputs) {
@@ -1047,7 +1047,7 @@ struct BtorDumper
 
 struct BtorBackend : public Backend {
 	BtorBackend() : Backend("btor", "write design to BTOR file") { }
-	
+
 	virtual void help()
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
@@ -1069,7 +1069,7 @@ struct BtorBackend : public Backend {
 
 		size_t argidx=1;
 		extra_args(f, filename, args, argidx);
-		
+
 		if (top_module_name.empty())
 			for (auto & mod_it:design->modules_)
 				if (mod_it.second->get_bool_attribute("\\top"))
@@ -1079,7 +1079,7 @@ struct BtorBackend : public Backend {
 		*f << stringf(";  %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);
 		*f << stringf("; BTOR Backend developed by Ahmed Irfan <irfan@fbk.eu> - Fondazione Bruno Kessler, Trento, Italy\n");
 		*f << stringf(";;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\n");
-		
+
 		std::vector<RTLIL::Module*> mod_list;
 
 		for (auto module_it : design->modules_)

backends/btor/verilog2btor.sh

@@ -17,11 +17,11 @@ FULL_PATH=$(readlink -f $1)
 DIR=$(dirname $FULL_PATH)
 
 ./yosys -q -p "
-read_verilog -sv $1; 
+read_verilog -sv $1;
-hierarchy -top $3; 
+hierarchy -top $3;
-hierarchy -libdir $DIR; 
+hierarchy -libdir $DIR;
-hierarchy -check; 
+hierarchy -check;
-proc; 
+proc;
 opt; opt_const -mux_undef; opt;
 rename -hide;;;
 #techmap -map +/pmux2mux.v;;
@@ -29,7 +29,7 @@ splice; opt;
 memory_dff -wr_only;
 memory_collect;;
 flatten;;
-memory_unpack; 
+memory_unpack;
 splitnets -driver;
 setundef -zero -undriven;
 opt;;;

backends/edif/edif.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

backends/ilang/ilang_backend.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -492,5 +492,5 @@ struct DumpPass : public Pass {
 		}
 	}
 } DumpPass;
- 
+
 PRIVATE_NAMESPACE_END

backends/ilang/ilang_backend.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

backends/intersynth/intersynth.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -159,7 +159,7 @@ struct IntersynthBackend : public Backend {
 				}
 			}
 
-			// Submodules: "std::set<string> celltypes_code" prevents duplicate cell types 
+			// Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
 			for (auto cell_it : module->cells_)
 			{
 				RTLIL::Cell *cell = cell_it.second;

backends/json/json.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

backends/smt2/smt2.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

backends/smv/smv.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

backends/spice/spice.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -120,7 +120,7 @@ struct SpiceBackend : public Backend {
 		log("Write the current design to an SPICE netlist file.\n");
 		log("\n");
 		log("    -big_endian\n");
-		log("        generate multi-bit ports in MSB first order \n");
+		log("        generate multi-bit ports in MSB first order\n");
 		log("        (default is LSB first)\n");
 		log("\n");
 		log("    -neg net_name\n");

backends/verilog/verilog_backend.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -967,7 +967,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			}
 		}
 		// Output verilog that looks something like this:
-		// reg [..] _3_; 
+		// reg [..] _3_;
 		// always @(posedge CLK2) begin
 		//   _3_ <= memory[D1ADDR];
 		//   if (A1EN)
@@ -1011,7 +1011,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 		return true;
 	}
-	
+
 	// FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_
 	// FIXME: $sr, $dlatch, $memrd, $memwr, $fsm
 

frontends/ast/ast.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -555,7 +555,7 @@ void AstNode::dumpVlog(FILE *f, std::string indent)
 		children[1]->dumpVlog(f, "");
 		fprintf(f, "}}");
 		break;
-	
+
 	if (0) { case AST_BIT_NOT:     txt = "~";  }
 	if (0) { case AST_REDUCE_AND:  txt = "&";  }
 	if (0) { case AST_REDUCE_OR:   txt = "|";  }

frontends/ast/ast.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/ast/dpicall.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/ast/genrtlil.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/ast/simplify.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -383,7 +383,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		detect_width_simple = true;
 		child_0_is_self_determined = true;
 		break;
-	
+
 	case AST_MEMRD:
 		detect_width_simple = true;
 		children_are_self_determined = true;

frontends/blif/blifparse.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/blif/blifparse.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/ilang/ilang_frontend.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/ilang/ilang_frontend.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/ilang/ilang_lexer.l

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/ilang/ilang_parser.y

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/liberty/liberty.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -40,7 +40,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
 
 	if (id_len == 0)
 		log_error("Expected identifier at `%s'.\n", expr);
-	
+
 	if (id_len == 1 && (*expr == '0' || *expr == '1'))
 		return *(expr++) == '0' ? RTLIL::State::S0 : RTLIL::State::S1;
 

frontends/verific/verific.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -947,6 +947,6 @@ struct VerificPass : public Pass {
 	}
 #endif
 } VerificPass;
- 
+
 YOSYS_NAMESPACE_END
 

frontends/verilog/const2ast.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/verilog/preproc.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -109,7 +109,7 @@ static std::string next_token(bool pass_newline = false)
 		}
 		return token;
 	}
-	
+
 	if (ch == ' ' || ch == '\t')
 	{
 		while ((ch = next_char()) != 0) {

frontends/verilog/verilog_frontend.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/verilog/verilog_frontend.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/verilog/verilog_lexer.l

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

frontends/verilog/verilog_parser.y

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -1054,13 +1054,13 @@ behavioral_stmt:
 	};
 
 case_type:
-	TOK_CASE { 
+	TOK_CASE {
 		case_type_stack.push_back(0);
 	} |
-	TOK_CASEX { 
+	TOK_CASEX {
 		case_type_stack.push_back('x');
 	} |
-	TOK_CASEZ { 
+	TOK_CASEZ {
 		case_type_stack.push_back('z');
 	};
 

frontends/vhdl2verilog/vhdl2verilog.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -178,6 +178,6 @@ struct Vhdl2verilogPass : public Pass {
 		log_pop();
 	}
 } Vhdl2verilogPass;
- 
+
 YOSYS_NAMESPACE_END
 

kernel/bitpattern.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -154,7 +154,7 @@ struct BitPatternPool
 	{
 		return database.empty();
 	}
-}; 
+};
 
 YOSYS_NAMESPACE_END
 

kernel/calc.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/cellaigs.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/cellaigs.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/celltypes.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/consteval.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/cost.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/driver.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/hashlib.h

@@ -1,5 +1,5 @@
 // This is free and unencumbered software released into the public domain.
-// 
+//
 // Anyone is free to copy, modify, publish, use, compile, sell, or
 // distribute this software, either in source code form or as a compiled
 // binary, for any purpose, commercial or non-commercial, and by any

kernel/log.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/log.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/macc.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/modtools.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/register.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -659,7 +659,7 @@ struct HelpPass : public Pass {
 		help();
 	}
 } HelpPass;
- 
+
 struct EchoPass : public Pass {
 	EchoPass() : Pass("echo", "turning echoing back of commands on and off") { }
 	virtual void help()
@@ -704,6 +704,6 @@ struct MinisatSatSolver : public SatSolver {
 		return new ezMiniSAT();
 	}
 } MinisatSatSolver;
- 
+
 YOSYS_NAMESPACE_END
 

kernel/register.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/rtlil.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -2870,7 +2870,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 
 	if (width_ > width)
 		remove(width, width_ - width);
-	
+
 	if (width_ < width) {
 		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
 		if (!is_signed)
@@ -3439,7 +3439,7 @@ RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
 	for (auto &it : cases)
 		new_switchrule->cases.push_back(it->clone());
 	return new_switchrule;
-	
+
 }
 
 RTLIL::SyncRule *RTLIL::SyncRule::clone() const
@@ -3471,7 +3471,7 @@ RTLIL::Process *RTLIL::Process::clone() const
 
 	for (auto &it : syncs)
 		new_proc->syncs.push_back(it->clone());
-	
+
 	return new_proc;
 }
 

kernel/rtlil.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -209,7 +209,7 @@ namespace RTLIL
 
 		char operator[](size_t i) const {
 			const char *p = c_str();
-			for (; i != 0; i--, p++) 
+			for (; i != 0; i--, p++)
 				log_assert(*p != 0);
 			return *p;
 		}
@@ -954,25 +954,25 @@ public:
 	RTLIL::Cell* addNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addPos (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addNeg (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
-                     
+
 	RTLIL::Cell* addAnd  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addOr   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addXor  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
-                     
+
 	RTLIL::Cell* addReduceAnd  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addReduceOr   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addReduceXor  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addReduceXnor (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addReduceBool (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
-                     
+
 	RTLIL::Cell* addShl    (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addShr    (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addSshl   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addSshr   (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addShift  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addShiftx (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
-                     
+
 	RTLIL::Cell* addLt  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addLe  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addEq  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
@@ -981,21 +981,21 @@ public:
 	RTLIL::Cell* addNex (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addGe  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addGt  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
-                     
+
 	RTLIL::Cell* addAdd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addSub (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addMul (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addDiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addMod (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addPow (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed = false, bool b_signed = false);
-                     
+
 	RTLIL::Cell* addLogicNot (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addLogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
 	RTLIL::Cell* addLogicOr  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
-                     
+
 	RTLIL::Cell* addMux  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y);
 	RTLIL::Cell* addPmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y);
-                     
+
 	RTLIL::Cell* addSlice  (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset);
 	RTLIL::Cell* addConcat (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
 	RTLIL::Cell* addLut    (RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut);

kernel/satgen.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/sigtools.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/utils.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -186,7 +186,7 @@ struct TopoSort
 				active_stack.pop_back();
 			active_cells.erase(n);
 		}
-		
+
 		marked_cells.insert(n);
 		sorted.push_back(n);
 	}

kernel/yosys.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

kernel/yosys.h

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

libs/ezsat/demo_bit.cc

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

libs/ezsat/demo_cmp.cc

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

libs/ezsat/demo_vec.cc

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

libs/ezsat/ezminisat.cc

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

libs/ezsat/ezminisat.h

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

libs/ezsat/ezsat.cc

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -1373,7 +1373,7 @@ int ezSAT::manyhot(const std::vector<int> &vec, int min_hot, int max_hot)
 
 	if (max_hot < 0)
 		max_hot = min_hot;
-	
+
 	std::vector<int> formula;
 	int M = max_hot+1, N = vec.size();
 	std::map<std::pair<int,int>, int> x;

libs/ezsat/ezsat.h

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

libs/ezsat/puzzle3d.cc

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -253,7 +253,7 @@ int main()
 	}
 	for (size_t i = 1; i < vecvec.size(); i++)
 		ez.assume(ez.ordered(vecvec[0], vecvec[1]));
-	
+
 	printf("Found and eliminated %d spatial symmetries.\n", int(symmetries.size()));
 	printf("Generated %d clauses over %d variables.\n", ez.numCnfClauses(), ez.numCnfVariables());
 

libs/ezsat/testbench.cc

@@ -2,11 +2,11 @@
  *  ezSAT -- A simple and easy to use CNF generator for SAT solvers
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -220,12 +220,12 @@ void test_count(uint32_t x)
 		fprintf(stderr, "FAILED 6bit-no-clipping test!\n");
 		abort();
 	}
-	
+
 	if (cv4 != sat.vec_count(v, 4, true)) {
 		fprintf(stderr, "FAILED 4bit-clipping test!\n");
 		abort();
 	}
-	
+
 	printf("ok.\n");
 }
 

libs/subcircuit/README

@@ -330,7 +330,7 @@ Mining for frequent SubCircuits
 
 The solver also contains a miner for frequent subcircuits. The following code
 fragment will find all frequent subcircuits with at least minNodes nodes and
-at most maxNodes nodes that occurs at least minMatches times: 
+at most maxNodes nodes that occurs at least minMatches times:
 
 	std::vector<SubCircuit::Solver::MineResult> results;
 	mySolver.mine(results, minNodes, maxNodes, minMatches);
@@ -370,7 +370,7 @@ This package also contains a small command-line tool called "scshell" that can
 be used for experimentation with the algorithm. This program reads a series of
 commands from stdin and reports its findings to stdout on exit.
 
-	$ ./scshell < test_macc22.txt 
+	$ ./scshell < test_macc22.txt
 
 	...
 

libs/subcircuit/subcircuit.cc

@@ -3,11 +3,11 @@
  *                algorithm for coarse grain logic networks
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

libs/subcircuit/subcircuit.h

@@ -3,11 +3,11 @@
  *                algorithm for coarse grain logic networks
  *
  *  Copyright (C) 2013  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -115,7 +115,7 @@ namespace SubCircuit
 
 	private:
 		SolverWorker *worker;
-	
+
 	protected:
 		virtual bool userCompareNodes(const std::string &needleGraphId, const std::string &needleNodeId, void *needleUserData,
 				const std::string &haystackGraphId, const std::string &haystackNodeId, void *haystackUserData, const std::map<std::string, std::string> &portMapping);

libs/subcircuit/test_large.spl

@@ -99,7 +99,7 @@ function makeGraph(seed, gates, primaryInputs, primaryOutputs)
 
 	foreach netDecl (unusedOutpus)
 		push primaryOutputs, netDecl;
-	
+
 	return code;
 }
 

manual/APPNOTE_010_Verilog_to_BLIF.tex

@@ -150,11 +150,11 @@ write_blif softusb_navre.blif
 \end{figure}
 
 The first and last line obviously read the Verilog file and write the BLIF
-file. 
+file.
 
 \medskip
 
-The 2nd line checks the design hierarchy and instantiates parametrized 
+The 2nd line checks the design hierarchy and instantiates parametrized
 versions of the modules in the design, if necessary. In the case of this
 simple design this is a no-op. However, as a general rule a synthesis script
 should always contain this command as first command after reading the input
@@ -174,7 +174,7 @@ instead of {\tt opt}.
 \item The command {\tt proc} converts {\it processes} (Yosys' internal
 representation of Verilog {\tt always}- and {\tt initial}-blocks) to circuits
 of multiplexers and storage elements (various types of flip-flops).
-\item The command {\tt memory} converts Yosys' internal representations of 
+\item The command {\tt memory} converts Yosys' internal representations of
 arrays and array accesses to multi-port block memories, and then maps this
 block memories to address decoders and flip-flops, unless the option {\tt -nomap}
 is used, in which case the multi-port block memories stay in the design

manual/APPNOTE_011_Design_Investigation.tex

@@ -256,7 +256,7 @@ Verilog file containing blackbox modules. There are two ways to load cell
 descriptions into Yosys: First the Verilog file for the cell library can be
 passed directly to the {\tt show} command using the {\tt -lib <filename>}
 option. Secondly it is possible to load cell libraries into the design with
-the {\tt read\_verilog -lib <filename>} command. The 2nd method has the great 
+the {\tt read\_verilog -lib <filename>} command. The 2nd method has the great
 advantage that the library only needs to be loaded once and can then be used
 in all subsequent calls to the {\tt show} command.
 
@@ -296,7 +296,7 @@ In addition to {\it what\/} to display one also needs to carefully decide
 {\it when\/} to display it, with respect to the synthesis flow. In general
 it is a good idea to troubleshoot a circuit in the earliest state in which
 a problem can be reproduced. So if, for example, the internal state before calling
-the {\tt techmap} command already fails to verify, it is better to troubleshoot 
+the {\tt techmap} command already fails to verify, it is better to troubleshoot
 the coarse-grain version of the circuit before {\tt techmap} than the gate-level
 circuit after {\tt techmap}.
 
@@ -316,7 +316,7 @@ yosys> ls
 1 modules:
   example
 
-yosys> cd example 
+yosys> cd example
 
 yosys [example]> ls
 
@@ -708,7 +708,7 @@ For example (see Fig.~\ref{submod} for the circuit diagram of {\tt selstage}):
 {\scriptsize
 \begin{verbatim}
    yosys [selstage]> eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
-   
+
    9. Executing EVAL pass (evaluate the circuit given an input).
    Full command line: eval -set s2,s1 4'b1001 -set d 4'hc -show n2 -show n1
    Eval result: \n2 = 2'10.
@@ -729,10 +729,10 @@ The {\tt -table} option can be used to create a truth table. For example:
 {\scriptsize
 \begin{verbatim}
    yosys [selstage]> eval -set-undef -set d[3:1] 0 -table s1,d[0]
-   
+
    10. Executing EVAL pass (evaluate the circuit given an input).
    Full command line: eval -set-undef -set d[3:1] 0 -table s1,d[0]
-   
+
      \s1 \d [0] |  \n1  \n2
     ---- ------ | ---- ----
     2'00    1'0 | 2'00 2'00
@@ -743,7 +743,7 @@ The {\tt -table} option can be used to create a truth table. For example:
     2'10    1'1 | 2'xx 2'10
     2'11    1'0 | 2'00 2'00
     2'11    1'1 | 2'xx 2'11
-   
+
    Assumend undef (x) value for the following singals: \s2
 \end{verbatim}
 }
@@ -780,11 +780,11 @@ Final proof equation: \ok = 1'1
 Solving problem with 2790 variables and 8241 clauses..
 SAT proof finished - model found: FAIL!
 
-   ______                   ___       ___       _ _            _ _ 
+   ______                   ___       ___       _ _            _ _
   (_____ \                 / __)     / __)     (_) |          | | |
    _____) )___ ___   ___ _| |__    _| |__ _____ _| | _____  __| | |
   |  ____/ ___) _ \ / _ (_   __)  (_   __|____ | | || ___ |/ _  |_|
-  | |   | |  | |_| | |_| || |       | |  / ___ | | || ____( (_| |_ 
+  | |   | |  | |_| | |_| || |       | |  / ___ | | || ____( (_| |_
   |_|   |_|   \___/ \___/ |_|       |_|  \_____|_|\_)_____)\____|_|
 
 
@@ -811,15 +811,15 @@ Final proof equation: \ok = 1'1
 Solving problem with 2790 variables and 8257 clauses..
 SAT proof finished - no model found: SUCCESS!
 
-                  /$$$$$$      /$$$$$$$$     /$$$$$$$    
+                  /$$$$$$      /$$$$$$$$     /$$$$$$$
-                 /$$__  $$    | $$_____/    | $$__  $$   
+                 /$$__  $$    | $$_____/    | $$__  $$
-                | $$  \ $$    | $$          | $$  \ $$   
+                | $$  \ $$    | $$          | $$  \ $$
-                | $$  | $$    | $$$$$       | $$  | $$   
+                | $$  | $$    | $$$$$       | $$  | $$
-                | $$  | $$    | $$__/       | $$  | $$   
+                | $$  | $$    | $$__/       | $$  | $$
-                | $$/$$ $$    | $$          | $$  | $$   
+                | $$/$$ $$    | $$          | $$  | $$
                 |  $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$
                  \____ $$$|__/|________/|__/|_______/|__/
-                       \__/                              
+                       \__/
 \end{lstlisting}
 \caption{Experiments with the miter circuit from Fig.~\ref{primetest}. The first attempt of proving that 31
 is prime failed because the SAT solver found a creative way of factorizing 31 using integer overflow.}
@@ -840,20 +840,20 @@ corresponding input values. For Example:
 {\scriptsize
 \begin{verbatim}
    yosys [selstage]> sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
-   
+
    11. Executing SAT pass (solving SAT problems in the circuit).
    Full command line: sat -show s1,s2,d -set s1 s2 -set n2,n1 4'b1001
-   
+
    Setting up SAT problem:
    Import set-constraint: \s1 = \s2
    Import set-constraint: { \n2 \n1 } = 4'1001
    Final constraint equation: { \n2 \n1 \s1 } = { 4'1001 \s2 }
    Imported 3 cells to SAT database.
    Import show expression: { \s1 \s2 \d }
-   
+
    Solving problem with 81 variables and 207 clauses..
    SAT solving finished - model found:
-   
+
      Signal Name                 Dec        Hex             Bin
      -------------------- ---------- ---------- ---------------
      \d                            9          9            1001

manual/APPNOTE_012_Verilog_to_BTOR.tex

@@ -182,7 +182,7 @@ file:
 
 \begin{figure}[H]
 \begin{lstlisting}[language=sh,numbers=none]
-$ boolector fsm.btor 
+$ boolector fsm.btor
 unsat
 \end{lstlisting}
  \renewcommand{\figurename}{Listing}
@@ -204,16 +204,16 @@ executed by {\tt verilog2btor.sh}.
 
 \begin{figure}[H]
 \begin{lstlisting}[language=sh]
-read_verilog -sv $1; 
+read_verilog -sv $1;
-hierarchy -top $3; hierarchy -libdir $DIR; 
+hierarchy -top $3; hierarchy -libdir $DIR;
-hierarchy -check; 
+hierarchy -check;
-proc; opt; 
+proc; opt;
 opt_const -mux_undef; opt;
 rename -hide;;;
 splice; opt;
 memory_dff -wr_only; memory_collect;;
 flatten;;
-memory_unpack; 
+memory_unpack;
 splitnets -driver;
 setundef -zero -undriven;
 opt;;;
@@ -242,7 +242,7 @@ line:
   collecting the memories to multi-port memories.
 \item Flattening the design to get only one module.
 \item Separating read and write memories.
-\item Splitting the signals that are partially assigned 
+\item Splitting the signals that are partially assigned
 \item Setting undef to zero value.
 \item Final optimization pass.
 \item Writing BTOR file.
@@ -259,10 +259,10 @@ modified Yosys script file:
 
 \begin{figure}[H]
 \begin{lstlisting}[language=sh,numbers=none]
-read_verilog -sv $1; 
+read_verilog -sv $1;
-hierarchy -top $3; hierarchy -libdir $DIR; 
+hierarchy -top $3; hierarchy -libdir $DIR;
-hierarchy -check; 
+hierarchy -check;
-proc; opt; 
+proc; opt;
 opt_const -mux_undef; opt;
 rename -hide;;;
 splice; opt;
@@ -294,7 +294,7 @@ module array(input clk);
     mem[counter] <= counter;
   end
 
-  assert property (!(counter > 8'd0) || 
+  assert property (!(counter > 8'd0) ||
     mem[counter - 8'd1] == counter - 8'd1);
 
 endmodule
@@ -422,7 +422,7 @@ Robert Brummayer and Armin Biere and Florian Lonsing, BTOR:
 Bit-Precise Modelling of Word-Level Problems for Model Checking\\
 \url{http://fmv.jku.at/papers/BrummayerBiereLonsing-BPR08.pdf}
 
-\bibitem{nuxmv} 
+\bibitem{nuxmv}
 Roberto Cavada and Alessandro Cimatti and Michele Dorigatti and
 Alberto Griggio and Alessandro Mariotti and Andrea Micheli and Sergio
 Mover and Marco Roveri and Stefano Tonetta, The nuXmv Symbolic Model

manual/CHAPTER_Appnotes.tex

@@ -5,7 +5,7 @@
 % \begin{fixme}
 % This appendix will cover some typical use-cases of Yosys in the form of application notes.
 % \end{fixme}
-% 
+%
 % \section{Synthesizing using a Cell Library in Liberty Format}
 % \section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
 % \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}

manual/CHAPTER_Basics.tex

@@ -56,8 +56,8 @@ and how they relate to different kinds of synthesis.
 Regardless of the way a lower level representation of a circuit is
 obtained (synthesis or manual design), the lower level representation is usually
 verified by comparing simulation results of the lower level and the higher level
-representation \footnote{In recent years formal equivalence 
+representation \footnote{In recent years formal equivalence
-checking also became an important verification method for validating RTL and 
+checking also became an important verification method for validating RTL and
 lower abstraction representation of the design.}.
 Therefore even if no synthesis is used, there must still be a simulatable
 representation of the circuit in all levels to allow for verification of the
@@ -270,7 +270,7 @@ signals.
 
 \subsection{Expressions in Verilog}
 
-In all situations where Verilog accepts a constant value or signal name, 
+In all situations where Verilog accepts a constant value or signal name,
 expressions using arithmetic operations such as
 \lstinline[language=Verilog]{+}, \lstinline[language=Verilog]{-} and \lstinline[language=Verilog]{*},
 boolean operations such as
@@ -470,7 +470,7 @@ optimizes the design. First of all because not all optimizations are applicable
 designs and all synthesis tasks. Some optimizations work (best) on a coarse-grained level
 (with complex cells such as adders or multipliers) and others work (best) on a fine-grained
 level (single bit gates). Some optimizations target area and others target speed.
-Some work well on large designs while others don't scale well and can only be applied 
+Some work well on large designs while others don't scale well and can only be applied
 to small designs.
 
 A good tool is capable of applying a wide range of optimizations at different

manual/CHAPTER_Eval/grep-it.sh

@@ -79,6 +79,6 @@ done
 # 	if [ $luts -gt 0 -a $luts_ys -gt 0 ]; then luts_p=$(( 100*luts_ys / luts )); else luts_p=NaN; fi
 # 	if [ $freq -gt 0 -a $freq_ys -gt 0 ]; then freq_p=$(( 100*freq_ys / freq )); else freq_p=NaN; fi
 # 	printf '%-30s %3s %3s %3s\n' $mod $regs_p $luts_p $freq_p
-# 
+#
 # done
 

manual/CHAPTER_Intro.tex

@@ -35,7 +35,7 @@ The proposed custom HDL synthesis tool should be licensed under a Free
 and Open Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL
 synthesis tool would have been needed as basis to build upon. The main advantages
 of choosing Verilog or VHDL is the ability to synthesize existing HDL code and
-to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool, 
+to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool,
 such a tool would have to provide a feature-complete implementation of the
 synthesizable HDL subset.
 
@@ -68,7 +68,7 @@ problem of implementing a HDL synthesis tool is approached in the case of
 Yosys.
 
 Chapter~\ref{chapter:overview} contains a more detailed overview of the
-implementation of Yosys. This chapter covers the data structures used in 
+implementation of Yosys. This chapter covers the data structures used in
 Yosys to represent a design in detail and is therefore recommended reading
 for everyone who is interested in understanding the Yosys internals.
 
@@ -81,7 +81,7 @@ is recommended reading for everyone who actually wants to read or write
 Yosys source code. The chapter concludes with an example loadable module
 for Yosys.
 
-Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} 
+Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap}
 cover three important pieces of the synthesis pipeline: The Verilog frontend,
 the optimization passes and the technology mapping to the target architecture,
 respectively.

manual/CHAPTER_Optimize.tex

@@ -241,7 +241,7 @@ by identifying the driver for the state signal.
 
 From there the {\tt \$mux}-tree driving the state register inputs is
 recursively traversed. All select inputs are control signals and the leaves of the
-{\tt \$mux}-tree are the states. The algorithm fails if a non-constant leaf 
+{\tt \$mux}-tree are the states. The algorithm fails if a non-constant leaf
 that is not the state signal itself is found.
 
 The list of control outputs is initialized with the bits from the state signal.

manual/CHAPTER_Overview.tex

@@ -307,11 +307,11 @@ process $proc$ff_with_en_and_async_reset.v:4$1
 	switch \reset
 		case 1'1
 			assign $0\q[0:0] 1'0
-		case 
+		case
 			switch \enable
 				case 1'1
 					assign $0\q[0:0] \d
-				case 
+				case
 			end
 	end
 	sync posedge \clock
@@ -338,7 +338,7 @@ An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig)
 and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a
 container for zero or more RTLIL::CaseRule objects.
 
-In the above example the lines $2 \dots 12$ are the root case. Here {\tt \$0\textbackslash{}q[0:0]} is first 
+In the above example the lines $2 \dots 12$ are the root case. Here {\tt \$0\textbackslash{}q[0:0]} is first
 assigned the old value {\tt \textbackslash{}q} as default value (line 2). The root case
 also contains an RTLIL::SwitchRule object (lines $3 \dots 12$). Such an object is very similar to the C {\tt switch}
 statement as it uses a control signal ({\tt \textbackslash{}reset} in this case) to determine
@@ -371,7 +371,7 @@ process $proc$ff_with_en_and_async_reset.v:4$1
 	switch \enable
 		case 1'1
 			assign $0\q[0:0] \d
-		case 
+		case
 	end
 	sync posedge \clock
 		update \q $0\q[0:0]
@@ -449,7 +449,7 @@ See Sec.~\ref{sec:memcells} for details about the memory cell types.
 Yosys reads and processes commands from synthesis scripts, command line arguments and
 an interactive command prompt. Yosys commands consist of a command name and an optional
 whitespace separated list of arguments. Commands are terminated using the newline character
-or a semicolon ({\tt ;}). Empty lines and lines starting with the hash sign ({\tt \#}) are ignored. 
+or a semicolon ({\tt ;}). Empty lines and lines starting with the hash sign ({\tt \#}) are ignored.
 See Sec.~\ref{sec:typusecase} for an example synthesis script.
 
 The command {\tt help} can be used to access the command reference manual.

manual/CHAPTER_Prog/stubnets.cc

@@ -1,5 +1,5 @@
 // This is free and unencumbered software released into the public domain.
-// 
+//
 // Anyone is free to copy, modify, publish, use, compile, sell, or
 // distribute this software, either in source code form or as a compiled
 // binary, for any purpose, commercial or non-commercial, and by any

manual/CHAPTER_StateOfTheArt/simlib_hana.v

@@ -1,4 +1,4 @@
-/* 
+/*
 Copyright (C) 2009-2010 Parvez Ahmad
 Written by Parvez Ahmad <parvez_ahmad@yahoo.co.uk>.
 
@@ -45,7 +45,7 @@ module AND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
 assign out = &in;
 
 endmodule
-    
+
 module AND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
 
 assign out = &in;
@@ -63,7 +63,7 @@ module OR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
 assign out = |in;
 
 endmodule
-    
+
 module OR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
 
 assign out = |in;
@@ -82,7 +82,7 @@ module NAND3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
 assign out = ~&in;
 
 endmodule
-    
+
 module NAND4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
 
 assign out = ~&in;
@@ -100,7 +100,7 @@ module NOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
 assign out = ~|in;
 
 endmodule
-    
+
 module NOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
 
 assign out = ~|in;
@@ -119,7 +119,7 @@ module XOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
 assign out = ^in;
 
 endmodule
-    
+
 module XOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
 
 assign out = ^in;
@@ -138,7 +138,7 @@ module XNOR3 #(parameter SIZE = 3) (input [SIZE-1:0] in, output out);
 assign out = ~^in;
 
 endmodule
-    
+
 module XNOR4 #(parameter SIZE = 4) (input [SIZE-1:0] in, output out);
 
 assign out = ~^in;
@@ -156,7 +156,7 @@ always @(in or enable)
 	       1'b1 : out = 2'b10;
 	    endcase
 	end
-endmodule	
+endmodule
 
 module DEC2 (input [1:0] in, input enable, output reg [3:0] out);
 
@@ -171,7 +171,7 @@ always @(in or enable)
 	       2'b11 : out = 4'b1000;
 	    endcase
 	end
-endmodule	
+endmodule
 
 module DEC3 (input [2:0] in, input enable, output reg [7:0] out);
 
@@ -190,7 +190,7 @@ always @(in or enable)
 	       3'b111 : out = 8'b10000000;
 	    endcase
 	end
-endmodule	
+endmodule
 
 module DEC4 (input [3:0] in, input enable, output reg [15:0] out);
 
@@ -217,7 +217,7 @@ always @(in or enable)
 	       4'b1111 : out = 16'b1000000000000000;
 	    endcase
 	end
-endmodule	
+endmodule
 module DEC5 (input [4:0] in, input enable, output reg [31:0] out);
 
 always @(in or enable)
@@ -259,7 +259,7 @@ always @(in or enable)
 	       5'b11111 : out = 32'b10000000000000000000000000000000;
 	    endcase
 	end
-endmodule	
+endmodule
 
 module DEC6 (input [5:0] in, input enable, output reg [63:0] out);
 
@@ -335,7 +335,7 @@ always @(in or enable)
 	       6'b111111 : out = 64'b1000000000000000000000000000000000000000000000000000000000000000;
 	    endcase
 	end
-endmodule	
+endmodule
 
 
 module MUX2(input [1:0] in, input select, output reg out);
@@ -345,7 +345,7 @@ always @( in or select)
 	    0: out = in[0];
 	    1: out = in[1];
 	endcase
-endmodule	
+endmodule
 
 
 module MUX4(input [3:0] in, input [1:0] select, output reg out);
@@ -357,7 +357,7 @@ always @( in or select)
 	    2: out = in[2];
 	    3: out = in[3];
 	endcase
-endmodule	
+endmodule
 
 
 module MUX8(input [7:0] in, input [2:0] select, output reg out);
@@ -373,7 +373,7 @@ always @( in or select)
 	    6: out = in[6];
 	    7: out = in[7];
 	endcase
-endmodule	
+endmodule
 
 module MUX16(input [15:0] in, input [3:0] select, output reg out);
 
@@ -396,7 +396,7 @@ always @( in or select)
 	    14: out = in[14];
 	    15: out = in[15];
 	endcase
-endmodule	
+endmodule
 
 module MUX32(input [31:0] in, input [4:0] select, output reg out);
 
@@ -435,7 +435,7 @@ always @( in or select)
 	    30: out = in[30];
 	    31: out = in[31];
 	endcase
-endmodule	
+endmodule
 
 module MUX64(input [63:0] in, input [5:0] select, output reg out);
 
@@ -506,7 +506,7 @@ always @( in or select)
 	    62: out = in[62];
 	    63: out = in[63];
 	endcase
-endmodule	
+endmodule
 
 module ADD1(input in1, in2, cin, output out, cout);
 
@@ -514,41 +514,41 @@ assign {cout, out} = in1 + in2 + cin;
 
 endmodule
 
-module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, 
+module ADD2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 + in2 + cin;
 
 endmodule
 
-module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, 
+module ADD4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 + in2 + cin;
 
 endmodule
 
-module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, 
+module ADD8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 + in2 + cin;
 
 endmodule
 
-module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, 
+module ADD16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 + in2 + cin;
 
 endmodule
 
-module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, 
+module ADD32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 + in2 + cin;
 
 endmodule
-module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, 
+module ADD64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 + in2 + cin;
@@ -561,41 +561,41 @@ assign {cout, out} = in1 - in2 - cin;
 
 endmodule
 
-module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, 
+module SUB2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 - in2 - cin;
 
 endmodule
 
-module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, 
+module SUB4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 - in2 - cin;
 
 endmodule
 
-module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, 
+module SUB8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 - in2 - cin;
 
 endmodule
 
-module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, 
+module SUB16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 - in2 - cin;
 
 endmodule
 
-module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, 
+module SUB32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 - in2 - cin;
 
 endmodule
-module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, 
+module SUB64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
     input cin, output [SIZE-1:0] out, output cout);
 
 assign {cout, out} = in1 - in2 - cin;
@@ -651,7 +651,7 @@ assign rem = in1%in2;
 
 endmodule
 
-module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2, 
+module DIV2 #(parameter SIZE = 2)(input [SIZE-1:0] in1, in2,
     output [SIZE-1:0] out, rem);
 
 assign out = in1/in2;
@@ -659,7 +659,7 @@ assign rem = in1%in2;
 
 endmodule
 
-module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2, 
+module DIV4 #(parameter SIZE = 4)(input [SIZE-1:0] in1, in2,
     output [SIZE-1:0] out, rem);
 
 assign out = in1/in2;
@@ -667,7 +667,7 @@ assign rem = in1%in2;
 
 endmodule
 
-module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2, 
+module DIV8 #(parameter SIZE = 8)(input [SIZE-1:0] in1, in2,
     output [SIZE-1:0] out, rem);
 
 assign out = in1/in2;
@@ -675,7 +675,7 @@ assign rem = in1%in2;
 
 endmodule
 
-module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2, 
+module DIV16 #(parameter SIZE = 16)(input [SIZE-1:0] in1, in2,
     output [SIZE-1:0] out, rem);
 
 assign out = in1/in2;
@@ -683,7 +683,7 @@ assign rem = in1%in2;
 
 endmodule
 
-module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2, 
+module DIV32 #(parameter SIZE = 32)(input [SIZE-1:0] in1, in2,
     output [SIZE-1:0] out, rem);
 
 assign out = in1/in2;
@@ -691,7 +691,7 @@ assign rem = in1%in2;
 
 endmodule
 
-module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2, 
+module DIV64 #(parameter SIZE = 64)(input [SIZE-1:0] in1, in2,
     output [SIZE-1:0] out, rem);
 
 assign out = in1/in2;
@@ -711,7 +711,7 @@ always @(posedge clk or posedge reset)
 	    q <= 0;
 	else
 	    q <= d;
-endmodule		
+endmodule
 
 module SFF(input d, clk, set, output reg q);
 always @(posedge clk or posedge set)
@@ -719,7 +719,7 @@ always @(posedge clk or posedge set)
 	    q <= 1;
 	else
 	    q <= d;
-endmodule		
+endmodule
 
 module RSFF(input d, clk, set, reset, output reg q);
 always @(posedge clk or posedge reset or posedge set)
@@ -745,30 +745,30 @@ module LATCH(input d, enable, output reg q);
 always @( d or enable)
     if(enable)
 	    q <= d;
-endmodule		
+endmodule
 
 module RLATCH(input d, reset, enable, output reg q);
 always @( d or enable or reset)
     if(enable)
 	    if(reset)
 		    q <= 0;
-		else	
+		else
 	        q <= d;
-endmodule		
+endmodule
 
 module LSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
 
 always @ (in, shift, val) begin
     if(shift)
 	    out = val;
-	else 
+	else
 	    out = in;
 end
 
 endmodule
 
 
-module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, 
+module LSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
     input [SIZE-1:0] shift, input val,
     output reg [SIZE-1:0] out);
 
@@ -776,58 +776,58 @@ always @(in or shift or val) begin
     out = in << shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end	
+end
 endmodule
 
-module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, 
+module LSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
     input [2:0] shift, input val, output reg [SIZE-1:0] out);
 
 always @(in or shift or val) begin
     out = in << shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end	
+end
 endmodule
 
 
-module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, 
+module LSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
     input [3:0] shift, input val, output reg [SIZE-1:0] out);
 
 always @(in or shift or val) begin
     out = in << shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end	
+end
 endmodule
 
-module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, 
+module LSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
     input [4:0] shift, input val, output reg [SIZE-1:0] out);
 
 always @(in or shift or val) begin
     out = in << shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end	
+end
 endmodule
 
-module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, 
+module LSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
     input [5:0] shift, input val, output reg [SIZE-1:0] out);
 
 always @(in or shift or val) begin
     out = in << shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end	
+end
 endmodule
 
-module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, 
+module LSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
     input [6:0] shift, input val, output reg [SIZE-1:0] out);
 
 always @(in or shift or val) begin
     out = in << shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } >> (SIZE-1-shift));
-end	
+end
 endmodule
 
 module RSHIFT1 #(parameter SIZE = 1)(input in, shift, val, output reg out);
@@ -841,7 +841,7 @@ end
 
 endmodule
 
-module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in, 
+module RSHIFT2 #(parameter SIZE = 2)(input [SIZE-1:0] in,
     input [SIZE-1:0] shift, input val,
     output reg [SIZE-1:0] out);
 
@@ -849,12 +849,12 @@ always @(in or shift or val) begin
     out = in >> shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end	
+end
 
 endmodule
 
 
-module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in, 
+module RSHIFT4 #(parameter SIZE = 4)(input [SIZE-1:0] in,
     input [2:0] shift, input val,
     output reg [SIZE-1:0] out);
 
@@ -862,10 +862,10 @@ always @(in or shift or val) begin
     out = in >> shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end	
+end
 endmodule
 
-module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in, 
+module RSHIFT8 #(parameter SIZE = 8)(input [SIZE-1:0] in,
     input [3:0] shift, input val,
     output reg [SIZE-1:0] out);
 
@@ -873,11 +873,11 @@ always @(in or shift or val) begin
     out = in >> shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end	
+end
 
 endmodule
 
-module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in, 
+module RSHIFT16 #(parameter SIZE = 16)(input [SIZE-1:0] in,
     input [4:0] shift, input val,
     output reg [SIZE-1:0] out);
 
@@ -885,11 +885,11 @@ always @(in or shift or val) begin
     out = in >> shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end	
+end
 endmodule
 
 
-module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in, 
+module RSHIFT32 #(parameter SIZE = 32)(input [SIZE-1:0] in,
     input [5:0] shift, input val,
     output reg [SIZE-1:0] out);
 
@@ -897,10 +897,10 @@ always @(in or shift or val) begin
     out = in >> shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end	
+end
 endmodule
 
-module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in, 
+module RSHIFT64 #(parameter SIZE = 64)(input [SIZE-1:0] in,
     input [6:0] shift, input val,
     output reg [SIZE-1:0] out);
 
@@ -908,10 +908,10 @@ always @(in or shift or val) begin
     out = in >> shift;
 	if(val)
 	    out = out | ({SIZE-1 {1'b1} } << (SIZE-1-shift));
-end	
+end
 endmodule
 
-module CMP1 #(parameter SIZE = 1) (input in1, in2, 
+module CMP1 #(parameter SIZE = 1) (input in1, in2,
     output reg equal, unequal, greater, lesser);
 
 always @ (in1 or in2) begin
@@ -920,7 +920,7 @@ always @ (in1 or in2) begin
 		unequal = 0;
 		greater = 0;
 		lesser = 0;
-	end	
+	end
 	else begin
 	    equal = 0;
 		unequal = 1;
@@ -928,17 +928,17 @@ always @ (in1 or in2) begin
 	    if(in1 < in2) begin
 		    greater = 0;
 		    lesser = 1;
-	    end	
+	    end
 	    else begin
 		    greater = 1;
 		    lesser = 0;
-	    end	
+	    end
-	end	
+	end
 end
 endmodule
 
 
-module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2, 
+module CMP2 #(parameter SIZE = 2) (input [SIZE-1:0] in1, in2,
     output reg equal, unequal, greater, lesser);
 
 always @ (in1 or in2) begin
@@ -947,7 +947,7 @@ always @ (in1 or in2) begin
 		unequal = 0;
 		greater = 0;
 		lesser = 0;
-	end	
+	end
 	else begin
 	    equal = 0;
 		unequal = 1;
@@ -955,16 +955,16 @@ always @ (in1 or in2) begin
 	    if(in1 < in2) begin
 		    greater = 0;
 		    lesser = 1;
-	    end	
+	    end
 	    else begin
 		    greater = 1;
 		    lesser = 0;
-	    end	
+	    end
-	end	
+	end
 end
 endmodule
 
-module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2, 
+module CMP4 #(parameter SIZE = 4) (input [SIZE-1:0] in1, in2,
     output reg equal, unequal, greater, lesser);
 
 always @ (in1 or in2) begin
@@ -973,7 +973,7 @@ always @ (in1 or in2) begin
 		unequal = 0;
 		greater = 0;
 		lesser = 0;
-	end	
+	end
 	else begin
 	    equal = 0;
 		unequal = 1;
@@ -981,16 +981,16 @@ always @ (in1 or in2) begin
 	    if(in1 < in2) begin
 		    greater = 0;
 		    lesser = 1;
-	    end	
+	    end
 	    else begin
 		    greater = 1;
 		    lesser = 0;
-	    end	
+	    end
-	end	
+	end
 end
 endmodule
 
-module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2, 
+module CMP8 #(parameter SIZE = 8) (input [SIZE-1:0] in1, in2,
     output reg equal, unequal, greater, lesser);
 
 always @ (in1 or in2) begin
@@ -999,7 +999,7 @@ always @ (in1 or in2) begin
 		unequal = 0;
 		greater = 0;
 		lesser = 0;
-	end	
+	end
 	else begin
 	    equal = 0;
 		unequal = 1;
@@ -1007,16 +1007,16 @@ always @ (in1 or in2) begin
 	    if(in1 < in2) begin
 		    greater = 0;
 		    lesser = 1;
-	    end	
+	    end
 	    else begin
 		    greater = 1;
 		    lesser = 0;
-	    end	
+	    end
-	end	
+	end
 end
 endmodule
 
-module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2, 
+module CMP16 #(parameter SIZE = 16) (input [SIZE-1:0] in1, in2,
     output reg equal, unequal, greater, lesser);
 
 always @ (in1 or in2) begin
@@ -1025,7 +1025,7 @@ always @ (in1 or in2) begin
 		unequal = 0;
 		greater = 0;
 		lesser = 0;
-	end	
+	end
 	else begin
 	    equal = 0;
 		unequal = 1;
@@ -1033,16 +1033,16 @@ always @ (in1 or in2) begin
 	    if(in1 < in2) begin
 		    greater = 0;
 		    lesser = 1;
-	    end	
+	    end
 	    else begin
 		    greater = 1;
 		    lesser = 0;
-	    end	
+	    end
-	end	
+	end
 end
 endmodule
 
-module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2, 
+module CMP32 #(parameter SIZE = 32) (input [SIZE-1:0] in1, in2,
     output reg equal, unequal, greater, lesser);
 
 always @ (in1 or in2) begin
@@ -1051,7 +1051,7 @@ always @ (in1 or in2) begin
 		unequal = 0;
 		greater = 0;
 		lesser = 0;
-	end	
+	end
 	else begin
 	    equal = 0;
 		unequal = 1;
@@ -1059,16 +1059,16 @@ always @ (in1 or in2) begin
 	    if(in1 < in2) begin
 		    greater = 0;
 		    lesser = 1;
-	    end	
+	    end
 	    else begin
 		    greater = 1;
 		    lesser = 0;
-	    end	
+	    end
-	end	
+	end
 end
 endmodule
 
-module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2, 
+module CMP64 #(parameter SIZE = 64) (input [SIZE-1:0] in1, in2,
     output reg equal, unequal, greater, lesser);
 
 always @ (in1 or in2) begin
@@ -1077,7 +1077,7 @@ always @ (in1 or in2) begin
 		unequal = 0;
 		greater = 0;
 		lesser = 0;
-	end	
+	end
 	else begin
 	    equal = 0;
 		unequal = 1;
@@ -1085,12 +1085,12 @@ always @ (in1 or in2) begin
 	    if(in1 < in2) begin
 		    greater = 0;
 		    lesser = 1;
-	    end	
+	    end
 	    else begin
 		    greater = 1;
 		    lesser = 0;
-	    end	
+	    end
-	end	
+	end
 end
 endmodule
 

manual/CHAPTER_StateOfTheArt/simlib_yosys.v

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

manual/CHAPTER_Verilog.tex

@@ -550,23 +550,23 @@ process $proc$<input>:1$1
   switch \in2
     case 1'1
       assign $1\out1[0:0] $logic_not$<input>:4$2_Y
-    case 
+    case
       assign $1\out1[0:0] \in1
   end
   switch \in3
     case 1'1
       assign $0\out2[0:0] \out2
-    case 
+    case
   end
   switch \in4
     case 1'1
       switch \in5
         case 1'1
           assign $0\out3[0:0] \in6
-        case 
+        case
           assign $0\out3[0:0] \in7
       end
-    case 
+    case
   end
   sync posedge \clock
     update \out1 $0\out1[0:0]

manual/PRESENTATION_ExAdv.tex

@@ -844,13 +844,13 @@ module adff2dff (CLK, ARST, D, Q);
     parameter CLK_POLARITY = 1;
     parameter ARST_POLARITY = 1;
     parameter ARST_VALUE = 0;
-    
+
     input CLK, ARST;
     input [WIDTH-1:0] D;
     output reg [WIDTH-1:0] Q;
-    
+
     wire [1023:0] _TECHMAP_DO_ = "proc";
-    
+
     wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
 \end{lstlisting}
 \vss}

manual/PRESENTATION_ExAdv/addshift_map.v

@@ -4,17 +4,17 @@ module \$add (A, B, Y);
   parameter A_WIDTH = 1;
   parameter B_WIDTH = 1;
   parameter Y_WIDTH = 1;
-  
+
   input [A_WIDTH-1:0] A;
   input [B_WIDTH-1:0] B;
   output [Y_WIDTH-1:0] Y;
-  
+
   parameter _TECHMAP_BITS_CONNMAP_ = 0;
   parameter _TECHMAP_CONNMAP_A_ = 0;
   parameter _TECHMAP_CONNMAP_B_ = 0;
-  
+
   wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
                         _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
-  
+
   assign Y = A << 1;
 endmodule

manual/PRESENTATION_ExAdv/red_or3x1_map.v

@@ -3,10 +3,10 @@ module \$reduce_or (A, Y);
     parameter A_SIGNED = 0;
     parameter A_WIDTH = 0;
     parameter Y_WIDTH = 0;
-    
+
     input [A_WIDTH-1:0] A;
     output [Y_WIDTH-1:0] Y;
-    
+
     function integer min;
         input integer a, b;
         begin
@@ -16,7 +16,7 @@ module \$reduce_or (A, Y);
                 min = b;
         end
     endfunction
-    
+
     genvar i;
     generate begin
         if (A_WIDTH == 0) begin

manual/PRESENTATION_ExAdv/sym_mul_map.v

@@ -4,12 +4,12 @@ module \$mul (A, B, Y);
     parameter A_WIDTH = 1;
     parameter B_WIDTH = 1;
     parameter Y_WIDTH = 1;
-    
+
     input [A_WIDTH-1:0] A;
     input [B_WIDTH-1:0] B;
     output [Y_WIDTH-1:0] Y;
-    
+
     wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
-    
+
     MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
 endmodule

manual/PRESENTATION_ExOth.tex

@@ -33,7 +33,7 @@ as {\tt \%ci} and {\tt \%co}, can be used to figure out how parts of the design
 are connected.
 
 \item
-Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used 
+Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
 to transform the design into an equivialent design that is easier to analyse.
 
 \item
@@ -115,7 +115,7 @@ The {\tt sat} command in Yosys can be used to perform Symbolic Model Checking.
 \end{frame}
 
 \begin{frame}[t]{Example: Formal Equivalence Checking (1/2)}
-Remember the following example? 
+Remember the following example?
 \vskip1em
 
 \vbox to 0cm{

manual/PRESENTATION_ExSyn.tex

@@ -22,7 +22,7 @@
 \item Convert remaining logic to bit-level logic functions
 \item Perform optimizations on bit-level logic functions
 \item Map bit-level logic gates and registers to cell library
-\item Write results to output file 
+\item Write results to output file
 \end{itemize}
 \end{frame}
 

manual/PRESENTATION_Intro/counter.ys

@@ -1,4 +1,4 @@
-# read design 
+# read design
 read_verilog counter.v
 hierarchy -check -top counter
 

manual/PRESENTATION_Prog.tex

@@ -325,7 +325,7 @@ Simulation models (i.e. {\it documentation\/} :-) for the internal cell library:
 
 \bigskip
 The lower-case cell types (such as {\tt \$and}) are parameterized cells of variable
-width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}. 
+width. This so-called {\it RTL Cells\/} are the cells described in {\tt simlib.v}.
 
 \bigskip
 The upper-case cell types (such as {\tt \$\_AND\_}) are single-bit cells that are not

manual/command-reference-manual.tex

@@ -2988,7 +2988,7 @@ from non-zero to zero in the test design.
 Write the current design to an SPICE netlist file.
 
     -big_endian
-        generate multi-bit ports in MSB first order 
+        generate multi-bit ports in MSB first order
         (default is LSB first)
 
     -neg net_name

misc/yosysjs/yosysjs.js

@@ -67,7 +67,7 @@ var YosysJS = new function() {
 		if (reference_element) {
 			if (reference_element.tagName == 'textarea')
 				ys.init_script = reference_element.value;
-		
+
 			if (reference_element.tagName == 'iframe') {
 				ys.iframe_element = reference_element;
 			} else {

passes/cmds/add.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -150,5 +150,5 @@ struct AddPass : public Pass {
 		}
 	}
 } AddPass;
- 
+
 PRIVATE_NAMESPACE_END

passes/cmds/check.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -150,5 +150,5 @@ struct CheckPass : public Pass {
 			log_error("Found %d problems in 'check -assert'.\n", counter);
 	}
 } CheckPass;
- 
+
 PRIVATE_NAMESPACE_END

passes/cmds/connect.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -185,5 +185,5 @@ struct ConnectPass : public Pass {
 			log_cmd_error("Expected -set, -unset, or -port.\n");
 	}
 } ConnectPass;
- 
+
 PRIVATE_NAMESPACE_END

passes/cmds/connwrappers.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -205,5 +205,5 @@ struct ConnwrappersPass : public Pass {
 				worker.work(design, mod_it.second);
 	}
 } ConnwrappersPass;
- 
+
 PRIVATE_NAMESPACE_END

passes/cmds/copy.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -55,5 +55,5 @@ struct CopyPass : public Pass {
 		design->add(new_mod);
 	}
 } CopyPass;
- 
+
 PRIVATE_NAMESPACE_END

passes/cmds/delete.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -140,5 +140,5 @@ struct DeletePass : public Pass {
 		}
 	}
 } DeletePass;
- 
+
 PRIVATE_NAMESPACE_END

passes/cmds/design.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR

passes/cmds/rename.cc

@@ -2,11 +2,11 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -228,5 +228,5 @@ struct RenamePass : public Pass {
 		}
 	}
 } RenamePass;
- 
+
 PRIVATE_NAMESPACE_END