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Fix handling of $shiftx in Verilog back-end 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-01-15 10:55:27 +01:00
parent 1d82a88e94
commit 6c5049f016
1 changed files with 6 additions and 3 deletions
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9
backends/verilog/verilog_backend.cc
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@ -709,11 +709,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == "$shiftx") if (cell->type == "$shiftx")
{ {
std::string temp_id = next_auto_id();
f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str());
dump_sigspec(f, cell->getPort("\\A"));
f << stringf(";\n");
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Y")); dump_sigspec(f, cell->getPort("\\Y"));
f << stringf(" = "); f << stringf(" = %s[", temp_id.c_str());
dump_sigspec(f, cell->getPort("\\A"));
f << stringf("[");
if (cell->getParam("\\B_SIGNED").as_bool()) if (cell->getParam("\\B_SIGNED").as_bool())
f << stringf("$signed("); f << stringf("$signed(");
dump_sigspec(f, cell->getPort("\\B")); dump_sigspec(f, cell->getPort("\\B"));