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write_xaiger: use sigmap bits more consistently

This commit is contained in:
Eddie Hung 2019-12-16 10:21:08 -08:00
parent c0339bbbf1
commit 6c340112fe
1 changed files with 4 additions and 5 deletions
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9
backends/aiger/xaiger.cc
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@ -294,7 +294,7 @@ struct XAigerWriter
output_bits.insert(b); output_bits.insert(b);
if (!cell_known) if (!cell_known)
inout_bits.insert(b); inout_bits.insert(I);
} }
} }
} }
@ -315,7 +315,7 @@ struct XAigerWriter
SigBit O = sigmap(b); SigBit O = sigmap(b);
if (O != b) if (O != b)
alias_map[O] = b; alias_map[O] = b;
input_bits.insert(b); input_bits.insert(O);
if (arrival) if (arrival)
arrival_times[b] = arrival; arrival_times[b] = arrival;
@ -542,9 +542,8 @@ struct XAigerWriter
undriven_bits.erase(bit); undriven_bits.erase(bit);
} }
// For inout ports, or keep-ed wires, then create a new wire with an // For inout ports, or keep-ed wires, which end up being both a PI and a
// $inout.out suffix, make it a PO driven by the existing inout, and // a PO then replace the PO with a new wire with the $inout.out suffix
// inherit existing inout's drivers
for (auto bit : inout_bits) { for (auto bit : inout_bits) {
RTLIL::Wire *wire = bit.wire; RTLIL::Wire *wire = bit.wire;
RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str()); RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());