mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1143 from YosysHQ/clifford/fix1135
Add "pmux2shiftx -norange"
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commit
6c210e5813
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@ -21,6 +21,7 @@ Yosys 0.8 .. Yosys 0.8-dev
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- Added "muxcover -dmux=<cost>"
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- Added "muxcover -dmux=<cost>"
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- Added "muxcover -nopartial"
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- Added "muxcover -nopartial"
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- Added "muxpack" pass
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- Added "muxpack" pass
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- Added "pmux2shiftx -norange"
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- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
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- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
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- Fixed sign extension of unsized constants with 'bx and 'bz MSB
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- Fixed sign extension of unsized constants with 'bx and 'bz MSB
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@ -221,6 +221,9 @@ struct Pmux2ShiftxPass : public Pass {
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log(" select strategy for one-hot encoded control signals\n");
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log(" select strategy for one-hot encoded control signals\n");
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log(" default: pmux\n");
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log(" default: pmux\n");
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log("\n");
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log("\n");
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log(" -norange\n");
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log(" disable $sub inference for \"range decoders\"\n");
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log("\n");
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}
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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{
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@ -230,6 +233,7 @@ struct Pmux2ShiftxPass : public Pass {
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bool optimize_onehot = true;
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bool optimize_onehot = true;
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bool verbose = false;
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bool verbose = false;
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bool verbose_onehot = false;
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bool verbose_onehot = false;
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bool norange = false;
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log_header(design, "Executing PMUX2SHIFTX pass.\n");
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log_header(design, "Executing PMUX2SHIFTX pass.\n");
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@ -270,6 +274,10 @@ struct Pmux2ShiftxPass : public Pass {
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verbose_onehot = true;
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verbose_onehot = true;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-norange") {
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norange = true;
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continue;
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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@ -559,7 +567,7 @@ struct Pmux2ShiftxPass : public Pass {
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int this_inv_delta = this_maxval - this_minval;
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int this_inv_delta = this_maxval - this_minval;
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bool this_inv = false;
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bool this_inv = false;
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if (this_delta != this_inv_delta)
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if (!norange && this_delta != this_inv_delta)
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this_inv = this_inv_delta < this_delta;
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this_inv = this_inv_delta < this_delta;
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else if (this_maxval != this_inv_maxval)
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else if (this_maxval != this_inv_maxval)
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this_inv = this_inv_maxval < this_maxval;
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this_inv = this_inv_maxval < this_maxval;
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@ -574,7 +582,7 @@ struct Pmux2ShiftxPass : public Pass {
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if (best_src_col < 0)
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if (best_src_col < 0)
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this_is_better = true;
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this_is_better = true;
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else if (this_delta != best_delta)
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else if (!norange && this_delta != best_delta)
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this_is_better = this_delta < best_delta;
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this_is_better = this_delta < best_delta;
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else if (this_maxval != best_maxval)
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else if (this_maxval != best_maxval)
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this_is_better = this_maxval < best_maxval;
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this_is_better = this_maxval < best_maxval;
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@ -656,7 +664,7 @@ struct Pmux2ShiftxPass : public Pass {
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// check density percentages
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// check density percentages
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Const offset(State::S0, GetSize(sig));
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Const offset(State::S0, GetSize(sig));
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if (absolute_density < min_density && range_density >= min_density)
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if (!norange && absolute_density < min_density && range_density >= min_density)
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{
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{
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offset = Const(min_choice, GetSize(sig));
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offset = Const(min_choice, GetSize(sig));
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log(" offset: %s\n", log_signal(offset));
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log(" offset: %s\n", log_signal(offset));
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@ -32,3 +32,13 @@ module pmux2shiftx_test (
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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module issue01135(input [7:0] i, output o);
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always @*
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case (i[6:3])
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4: o <= i[0];
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3: o <= i[2];
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7: o <= i[3];
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default: o <= 1'b0;
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endcase
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endmodule
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@ -1,4 +1,7 @@
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read_verilog pmux2shiftx.v
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read_verilog pmux2shiftx.v
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design -save read
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hierarchy -top pmux2shiftx_test
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prep
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prep
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design -save gold
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design -save gold
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@ -21,8 +24,16 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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sat -verify -prove-asserts -show-ports miter
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design -load gold
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#design -load gold
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stat
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#stat
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#
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#design -load gate
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#stat
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design -load gate
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design -load read
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stat
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hierarchy -top issue01135
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proc
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pmux2shiftx -norange
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opt -full
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select -assert-count 0 t:$shift*
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select -assert-count 1 t:$pmux
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