From 9018d06a33d2d66f57ad825053c31f85417339a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 19 Sep 2024 11:21:09 +0200 Subject: [PATCH 1/3] quicklogic: Avoid carry chains in division mapping The default mapping rules for division-like operations (div/divfloor/ mod/modfloor) invoke subtractions which can get mapped to carry chains in FPGA flows. Optimizations across carry chains are weak, so in practice this ends up too costly compared to implementing the division purely in soft logic. For this reason arrange for `techmap.v` ignoring division operations under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry chains for divisions. --- techlibs/common/techmap.v | 3 ++- techlibs/quicklogic/synth_quicklogic.cc | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index 68b276588..119296147 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -304,6 +304,7 @@ endmodule // Divide and Modulo // -------------------------------------------------------- +`ifndef NODIV module \$__div_mod_u (A, B, Y, R); parameter WIDTH = 1; @@ -531,7 +532,7 @@ module _90_modfloor (A, B, Y); .R(Y) ); endmodule - +`endif // -------------------------------------------------------- // Power diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 0e7aaa752..76ef44570 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -266,7 +266,8 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("map_gates")) { if (inferAdder && family == "qlf_k6n10f") { - run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)"); + run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v -D NODIV", "(unless -no_adder)"); + run("techmap", "(unless -no_adder)"); } else { run("techmap"); } From 13ecbd5c76b37b8dc14b945a63d1a54b1fcfeced Mon Sep 17 00:00:00 2001 From: Lofty Date: Thu, 3 Oct 2024 20:05:28 +0100 Subject: [PATCH 2/3] quicklogic: test that dividing by a constant does not infer carry chains --- tests/arch/quicklogic/qlf_k6n10f/div.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/div.ys diff --git a/tests/arch/quicklogic/qlf_k6n10f/div.ys b/tests/arch/quicklogic/qlf_k6n10f/div.ys new file mode 100644 index 000000000..5ca5b3051 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/div.ys @@ -0,0 +1,14 @@ +# division by constants should not infer carry chains. +read_verilog < Date: Mon, 7 Oct 2024 15:26:48 +0200 Subject: [PATCH 3/3] quicklogic: Relax the LUT number test --- tests/arch/quicklogic/qlf_k6n10f/div.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/div.ys b/tests/arch/quicklogic/qlf_k6n10f/div.ys index 5ca5b3051..dd5de9d3a 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/div.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/div.ys @@ -10,5 +10,5 @@ EOF equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 26 t:$lut +select -assert-max 100 t:$lut select -assert-none t:$lut %% t:* %D