mirror of https://github.com/YosysHQ/yosys.git
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
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@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
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if (width_ != other.width_)
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return false;
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// Without this, SigSpec() == SigSpec(State::S0, 0) will fail
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// since the RHS will contain one SigChunk of width 0 causing
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// the size check below to fail
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if (width_ == 0)
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return true;
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pack();
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other.pack();
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