riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Make TimingInfo::TimingInfo(SigBit) constructor explicit

This commit is contained in:
Eddie Hung 2020-02-18 11:02:28 -08:00
parent 9dcf204dec
commit 6bb3d9f9c0
3 changed files with 9 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/aiger/xaiger.cc
View File

@ -263,7 +263,7 @@ struct XAigerWriter
continue; continue;
for (int i = 0; i < GetSize(conn.second); i++) { for (int i = 0; i < GetSize(conn.second); i++) {
auto d = t.at(SigBit(port_wire,i), 0); auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
if (d == 0) if (d == 0)
continue; continue;

9
kernel/timinginfo.h
View File

@ -31,8 +31,9 @@ struct TimingInfo
{ {
RTLIL::IdString name; RTLIL::IdString name;
int offset; int offset;
NameBit() {} NameBit() : offset(0) {}
NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {} NameBit(const RTLIL::IdString name, int offset) : name(name), offset(offset) {}
explicit NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; } bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
bool operator!=(const NameBit& nb) const { return !operator==(nb); } bool operator!=(const NameBit& nb) const { return !operator==(nb); }
unsigned int hash() const { return mkhash_add(name.hash(), offset); } unsigned int hash() const { return mkhash_add(name.hash(), offset); }
@ -127,7 +128,7 @@ struct TimingInfo
continue; continue;
} }
for (const auto &d : dst) { for (const auto &d : dst) {
auto &v = t.arrival[d]; auto &v = t.arrival[NameBit(d)];
v = std::max(v, max); v = std::max(v, max);
} }
} }
@ -151,7 +152,7 @@ struct TimingInfo
continue; continue;
} }
for (const auto &s : src) { for (const auto &s : src) {
auto &v = t.required[s]; auto &v = t.required[NameBit(s)];
v = std::max(v, max); v = std::max(v, max);
} }
} }

6
passes/techmap/abc9_ops.cc
View File

@ -440,7 +440,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); SigSpec O = module->addWire(NEW_ID, GetSize(conn.second));
for (int i = 0; i < GetSize(conn.second); i++) { for (int i = 0; i < GetSize(conn.second); i++) {
auto d = t.at(SigBit(port_wire,i), 0); auto d = t.at(TimingInfo::NameBit(conn.first,i), 0);
if (d == 0) if (d == 0)
continue; continue;
@ -582,7 +582,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
else else
ss << " "; ss << " ";
log_assert(GetSize(wire) == 1); log_assert(GetSize(wire) == 1);
auto it = t.find(SigBit(wire,0)); auto it = t.find(TimingInfo::NameBit(port_name,0));
if (it == t.end()) if (it == t.end())
// Assume that no setup time means zero // Assume that no setup time means zero
ss << 0; ss << 0;
@ -680,7 +680,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
first = false; first = false;
else else
ss << " "; ss << " ";
auto jt = t.find(std::make_pair(i,o)); auto jt = t.find(std::make_pair(TimingInfo::NameBit(i),TimingInfo::NameBit(o)));
if (jt == t.end()) if (jt == t.end())
ss << "-"; ss << "-";
else else