This commit is contained in:
Eddie Hung 2019-09-27 17:00:19 -07:00
parent fd0e3a2c43
commit 6b9f90de78
1 changed files with 1 additions and 1 deletions

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@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
{ {
std::vector<RTLIL::Cell*> result; std::vector<RTLIL::Cell*> result;
result.reserve(wires_.size()); result.reserve(cells_.size());
for (auto &it : cells_) for (auto &it : cells_)
if (design->selected(this, it.second)) if (design->selected(this, it.second))
result.push_back(it.second); result.push_back(it.second);