diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 53359bd7b..55c494996 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -615,6 +615,7 @@ struct BtorWorker { int abits = cell->getParam("\\ABITS").as_int(); int width = cell->getParam("\\WIDTH").as_int(); + int nwords = cell->getParam("\\SIZE").as_int(); int rdports = cell->getParam("\\RD_PORTS").as_int(); int wrports = cell->getParam("\\WR_PORTS").as_int(); @@ -641,6 +642,52 @@ struct BtorWorker int data_sid = get_bv_sid(width); int bool_sid = get_bv_sid(1); int sid = get_mem_sid(abits, width); + + Const initdata = cell->getParam("\\INIT"); + initdata.exts(nwords*width); + int nid_init_val = -1; + + if (!initdata.is_fully_undef()) + { + bool constword = true; + Const firstword = initdata.extract(0, width); + + for (int i = 1; i < nwords; i++) { + Const thisword = initdata.extract(i*width, width); + if (thisword != firstword) { + constword = false; + break; + } + } + + if (constword) + { + if (verbose) + btorf("; initval = %s\n", log_signal(firstword)); + nid_init_val = get_sig_nid(firstword); + } + else + { + int nid_init_val = next_nid++; + btorf("%d state %d\n", nid_init_val, sid); + + for (int i = 0; i < nwords; i++) { + Const thisword = initdata.extract(i*width, width); + if (thisword.is_fully_undef()) + continue; + Const thisaddr(i, abits); + int nid_thisword = get_sig_nid(thisword); + int nid_thisaddr = get_sig_nid(thisaddr); + int last_nid_init_val = nid_init_val; + nid_init_val = next_nid++; + if (verbose) + btorf("; initval[%d] = %s\n", i, log_signal(thisword)); + btorf("%d write %d %d %d %d\n", nid_init_val, sid, last_nid_init_val, nid_thisaddr, nid_thisword); + } + } + } + + int nid = next_nid++; int nid_head = nid; @@ -649,6 +696,12 @@ struct BtorWorker else btorf("%d state %d %s\n", nid, sid, log_id(cell)); + if (nid_init_val >= 0) + { + int nid_init = next_nid++; + btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val); + } + if (asyncwr) { for (int port = 0; port < wrports; port++) @@ -932,9 +985,8 @@ struct BtorWorker btorf_push(stringf("output %s", log_id(wire))); - int sid = get_bv_sid(GetSize(wire)); int nid = get_sig_nid(wire); - btorf("%d output %d %d %s\n", next_nid++, sid, nid, log_id(wire)); + btorf("%d output %d %s\n", next_nid++, nid, log_id(wire)); btorf_pop(stringf("output %s", log_id(wire))); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index d0fa88890..b3214579d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3237,7 +3237,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed) remove(width, width_ - width); if (width_ < width) { - RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0; + RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx; if (!is_signed) padding = RTLIL::State::S0; while (width_ < width) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 01323d112..52496e702 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -546,6 +546,14 @@ struct RTLIL::Const return ret; } + void extu(int width) { + bits.resize(width, RTLIL::State::S0); + } + + void exts(int width) { + bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back()); + } + inline unsigned int hash() const { unsigned int h = mkhash_init; for (auto b : bits) diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index cf4095d06..c38eabaee 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -542,7 +542,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, } // assign write ports - + pair wr_clkdom; for (int cell_port_i = 0, bram_port_i = 0; cell_port_i < wr_ports; cell_port_i++) { bool clken = wr_clken[cell_port_i] == State::S1; @@ -552,7 +552,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram, pair clkdom(clksig, clkpol); if (!clken) clkdom = pair(State::S1, false); - + wr_clkdom = clkdom; log(" Write port #%d is in clock domain %s%s.\n", cell_port_i, clkdom.second ? "" : "!", clken ? log_signal(clkdom.first) : "~async~"); @@ -718,7 +718,13 @@ grow_read_ports:; if (read_transp.count(pi.transp) && read_transp.at(pi.transp) != transp) { if (match.make_transp && wr_ports <= 1) { pi.make_transp = true; - enable_make_transp = true; + if (pi.clocks != 0) { + if (wr_ports == 1 && wr_clkdom != clkdom) { + log(" Bram port %c%d.%d cannot have soft transparency logic added as read and write clock domains differ.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1); + goto skip_bram_rport; + } + enable_make_transp = true; + } } else { log(" Bram port %c%d.%d has incompatible read transparency.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1); goto skip_bram_rport; @@ -913,17 +919,18 @@ grow_read_ports:; } else { SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits); c->setPort(stringf("\\%sDATA", pf), bram_dout); - - if (pi.make_outreg) { + if (pi.make_outreg && pi.make_transp) { + log(" Moving output register to address for transparent port %c%d.%d.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1); + SigSpec sig_addr_q = module->addWire(NEW_ID, bram.abits); + module->addDff(NEW_ID, pi.sig_clock, sig_addr, sig_addr_q, pi.effective_clkpol); + c->setPort(stringf("\\%sADDR", pf), sig_addr_q); + } else if (pi.make_outreg) { SigSpec bram_dout_q = module->addWire(NEW_ID, bram.dbits); if (!pi.sig_en.empty()) bram_dout = module->Mux(NEW_ID, bram_dout_q, bram_dout, pi.sig_en); module->addDff(NEW_ID, pi.sig_clock, bram_dout, bram_dout_q, pi.effective_clkpol); bram_dout = bram_dout_q; - } - - if (pi.make_transp) - { + } else if (pi.make_transp) { log(" Adding extra logic for transparent port %c%d.%d.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1); SigSpec transp_en_d = module->Mux(NEW_ID, SigSpec(0, make_transp_enbits), diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc index 4eced2ff1..fc3ac879e 100644 --- a/passes/sat/Makefile.inc +++ b/passes/sat/Makefile.inc @@ -11,4 +11,5 @@ OBJS += passes/sat/async2sync.o OBJS += passes/sat/supercover.o OBJS += passes/sat/fmcombine.o OBJS += passes/sat/mutate.o +OBJS += passes/sat/cutpoint.o diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc new file mode 100644 index 000000000..3a38ebac0 --- /dev/null +++ b/passes/sat/cutpoint.cc @@ -0,0 +1,164 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct CutpointPass : public Pass { + CutpointPass() : Pass("cutpoint", "add hi/lo cover cells for each wire bit") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" cutpoint [options] [selection]\n"); + log("\n"); + log("This command adds formal cut points to the design.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + // bool flag_noinit = false; + + log_header(design, "Executing CUTPOINT pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // if (args[argidx] == "-noinit") { + // flag_noinit = true; + // continue; + // } + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + { + if (design->selected_whole_module(module->name)) { + log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module)); + module->new_connections(std::vector()); + for (auto cell : vector(module->cells())) + module->remove(cell); + vector output_wires; + for (auto wire : module->wires()) + if (wire->port_output) + output_wires.push_back(wire); + for (auto wire : output_wires) + module->connect(wire, module->Anyseq(NEW_ID, GetSize(wire))); + continue; + } + + SigMap sigmap(module); + pool cutpoint_bits; + + for (auto cell : module->selected_cells()) { + if (cell->type == "$anyseq") + continue; + log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell)); + for (auto &conn : cell->connections()) { + if (cell->output(conn.first)) + module->connect(conn.second, module->Anyseq(NEW_ID, GetSize(conn.second))); + } + module->remove(cell); + } + + for (auto wire : module->selected_wires()) { + if (wire->port_output) { + log("Making output wire %s.%s a cutpoint.\n", log_id(module), log_id(wire)); + Wire *new_wire = module->addWire(NEW_ID, wire); + module->swap_names(wire, new_wire); + module->connect(new_wire, module->Anyseq(NEW_ID, GetSize(new_wire))); + wire->port_id = 0; + wire->port_input = false; + wire->port_output = false; + continue; + } + log("Making wire %s.%s a cutpoint.\n", log_id(module), log_id(wire)); + for (auto bit : sigmap(wire)) + cutpoint_bits.insert(bit); + } + + if (!cutpoint_bits.empty()) + { + for (auto cell : module->cells()) { + for (auto &conn : cell->connections()) { + if (!cell->output(conn.first)) + continue; + SigSpec sig = sigmap(conn.second); + int bit_count = 0; + for (auto &bit : sig) { + if (cutpoint_bits.count(bit)) + bit_count++; + } + if (bit_count == 0) + continue; + SigSpec dummy = module->addWire(NEW_ID, bit_count); + bit_count = 0; + for (auto &bit : sig) { + if (cutpoint_bits.count(bit)) + bit = dummy[bit_count++]; + } + cell->setPort(conn.first, sig); + } + } + + vector rewrite_wires; + for (auto wire : module->wires()) { + if (!wire->port_input) + continue; + int bit_count = 0; + for (auto &bit : sigmap(wire)) + if (cutpoint_bits.count(bit)) + bit_count++; + if (bit_count) + rewrite_wires.push_back(wire); + } + + for (auto wire : rewrite_wires) { + Wire *new_wire = module->addWire(NEW_ID, wire); + SigSpec lhs, rhs, sig = sigmap(wire); + for (int i = 0; i < GetSize(sig); i++) + if (!cutpoint_bits.count(sig[i])) { + lhs.append(SigBit(wire, i)); + rhs.append(SigBit(new_wire, i)); + } + if (GetSize(lhs)) + module->connect(lhs, rhs); + module->swap_names(wire, new_wire); + wire->port_id = 0; + wire->port_input = false; + wire->port_output = false; + } + + SigSpec sig(cutpoint_bits); + sig.sort_and_unify(); + + for (auto chunk : sig.chunks()) { + SigSpec s(chunk); + module->connect(s, module->Anyseq(NEW_ID, GetSize(s))); + } + } + } + } +} CutpointPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 9621d2855..c50678c51 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -46,6 +46,8 @@ struct mutate_opts_t { IdString ctrl_name; int ctrl_width = -1, ctrl_value = -1; + bool none = false; + int pick_cover_prcnt = 80; int weight_cover = 500; @@ -422,8 +424,9 @@ void database_reduce(std::vector &database, const mutate_opts_t &opts, log("Covered %d/%d wire bits (%.2f%%).\n", covered_wirebit_cnt, GetSize(coverdb.wirebit_db), 100.0 * covered_wirebit_cnt / GetSize(coverdb.wirebit_db)); } -void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, int N) +void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, const string &srcsfile, int N) { + pool sources; std::vector database; xs128_t rng(opts.seed); @@ -497,6 +500,9 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena entry.wirebit = bit.offset; } + if (!srcsfile.empty()) + sources.insert(entry.src.begin(), entry.src.end()); + entry.mode = "inv"; database_add(database, opts, entry); @@ -522,10 +528,20 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena log("Raw database size: %d\n", GetSize(database)); if (N != 0) { - database_reduce(database, opts, N, rng); + database_reduce(database, opts, opts.none ? N-1 : N, rng); log("Reduced database size: %d\n", GetSize(database)); } + if (!srcsfile.empty()) { + std::ofstream sout; + sout.open(srcsfile, std::ios::out | std::ios::trunc); + if (!sout.is_open()) + log_error("Could not open file \"%s\" with write access.\n", srcsfile.c_str()); + sources.sort(); + for (auto &s : sources) + sout << s << std::endl; + } + std::ofstream fout; if (!filename.empty()) { @@ -536,6 +552,17 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena int ctrl_value = opts.ctrl_value; + if (opts.none) { + string str = "mutate"; + if (!opts.ctrl_name.empty()) + str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++); + str += " -mode none"; + if (filename.empty()) + log("%s\n", str.c_str()); + else + fout << str << std::endl; + } + for (auto &entry : database) { string str = "mutate"; if (!opts.ctrl_name.empty()) @@ -710,9 +737,15 @@ struct MutatePass : public Pass { log(" -o filename\n"); log(" Write list to this file instead of console output\n"); log("\n"); + log(" -s filename\n"); + log(" Write a list of all src tags found in the design to the specified file\n"); + log("\n"); log(" -seed N\n"); log(" RNG seed for selecting mutations\n"); log("\n"); + log(" -none\n"); + log(" Include a \"none\" mutation in the output\n"); + log("\n"); log(" -ctrl name width value\n"); log(" Add -ctrl options to the output. Use 'value' for first mutation, then\n"); log(" simply count up from there.\n"); @@ -761,6 +794,7 @@ struct MutatePass : public Pass { { mutate_opts_t opts; string filename; + string srcsfile; int N = -1; log_header(design, "Executing MUTATE pass.\n"); @@ -776,10 +810,18 @@ struct MutatePass : public Pass { filename = args[++argidx]; continue; } + if (args[argidx] == "-s" && argidx+1 < args.size()) { + srcsfile = args[++argidx]; + continue; + } if (args[argidx] == "-seed" && argidx+1 < args.size()) { opts.seed = atoi(args[++argidx].c_str()); continue; } + if (args[argidx] == "-none") { + opts.none = true; + continue; + } if (args[argidx] == "-mode" && argidx+1 < args.size()) { opts.mode = args[++argidx]; continue; @@ -879,7 +921,16 @@ struct MutatePass : public Pass { extra_args(args, argidx, design); if (N >= 0) { - mutate_list(design, opts, filename, N); + mutate_list(design, opts, filename, srcsfile, N); + return; + } + + if (opts.mode == "none") { + if (!opts.ctrl_name.empty()) { + Module *topmod = opts.module.empty() ? design->top_module() : design->module(opts.module); + if (topmod) + mutate_ctrl_sig(topmod, opts.ctrl_name, opts.ctrl_width); + } return; } diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc index 3927a657b..8eadd8735 100644 --- a/passes/techmap/libparse.cc +++ b/passes/techmap/libparse.cc @@ -24,6 +24,7 @@ #include #include #include +#include #ifndef FILTERLIB #include "kernel/log.h" @@ -86,15 +87,17 @@ int LibertyParser::lexer(std::string &str) { int c; + // eat whitespace do { c = f.get(); } while (c == ' ' || c == '\t' || c == '\r'); - if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']') { + // search for identifiers, numbers, plus or minus. + if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') { str = c; while (1) { c = f.get(); - if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']') + if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') str += c; else break; @@ -111,6 +114,8 @@ int LibertyParser::lexer(std::string &str) } } + // if it wasn't an identifer, number of array range, + // maybe it's a string? if (c == '"') { str = ""; while (1) { @@ -125,9 +130,10 @@ int LibertyParser::lexer(std::string &str) return 'v'; } + // if it wasn't a string, perhaps it's a comment or a forward slash? if (c == '/') { c = f.get(); - if (c == '*') { + if (c == '*') { // start of '/*' block comment int last_c = 0; while (c > 0 && (last_c != '*' || c != '/')) { last_c = c; @@ -136,7 +142,7 @@ int LibertyParser::lexer(std::string &str) line++; } return lexer(str); - } else if (c == '/') { + } else if (c == '/') { // start of '//' line comment while (c > 0 && c != '\n') c = f.get(); line++; @@ -144,9 +150,10 @@ int LibertyParser::lexer(std::string &str) } f.unget(); // fprintf(stderr, "LEX: char >>/<<\n"); - return '/'; + return '/'; // a single '/' charater. } + // check for a backslash if (c == '\\') { c = f.get(); if (c == '\r') @@ -157,11 +164,15 @@ int LibertyParser::lexer(std::string &str) return '\\'; } + // check for a new line if (c == '\n') { line++; return 'n'; } + // anything else, such as ';' will get passed + // through as literal items. + // if (c >= 32 && c < 255) // fprintf(stderr, "LEX: char >>%c<<\n", c); // else @@ -191,12 +202,11 @@ LibertyAst *LibertyParser::parse() { tok = lexer(str); - if (tok == ';') + // allow both ';' and new lines to + // terminate a statement. + if ((tok == ';') || (tok == 'n')) break; - if (tok == 'n') - continue; - if (tok == ':' && ast->value.empty()) { tok = lexer(ast->value); if (tok != 'v') @@ -210,7 +220,12 @@ LibertyAst *LibertyParser::parse() ast->value += str; tok = lexer(str); } - if (tok == ';') + + // In a liberty file, all key : value pairs should end in ';' + // However, there are some liberty files in the wild that + // just have a newline. We'll be kind and accept a newline + // instead of the ';' too.. + if ((tok == ';') || (tok == 'n')) break; else error(); @@ -225,6 +240,48 @@ LibertyAst *LibertyParser::parse() continue; if (tok == ')') break; + + // FIXME: the AST needs to be extended to store + // these vector ranges. + if (tok == '[') + { + // parse vector range [A] or [A:B] + std::string arg; + tok = lexer(arg); + if (tok != 'v') + { + // expected a vector array index + error("Expected a number."); + } + else + { + // fixme: check for number A + } + tok = lexer(arg); + // optionally check for : in case of [A:B] + // if it isn't we just expect ']' + // as we have [A] + if (tok == ':') + { + tok = lexer(arg); + if (tok != 'v') + { + // expected a vector array index + error("Expected a number."); + } + else + { + // fixme: check for number B + tok = lexer(arg); + } + } + // expect a closing bracket of array range + if (tok != ']') + { + error("Expected ']' on array range."); + } + continue; + } if (tok != 'v') error(); ast->args.push_back(arg); @@ -255,6 +312,14 @@ void LibertyParser::error() log_error("Syntax error in liberty file on line %d.\n", line); } +void LibertyParser::error(const std::string &str) +{ + std::stringstream ss; + ss << "Syntax error in liberty file on line " << line << ".\n"; + ss << " " << str << "\n"; + log_error("%s", ss.str().c_str()); +} + #else void LibertyParser::error() @@ -263,25 +328,34 @@ void LibertyParser::error() exit(1); } +void LibertyParser::error(const std::string &str) +{ + std::stringstream ss; + ss << "Syntax error in liberty file on line " << line << ".\n"; + ss << " " << str << "\n"; + printf("%s", ss.str().c_str()); + exit(1); +} + /**** BEGIN: http://svn.clifford.at/tools/trunk/examples/check.h ****/ #define CHECK_NV(result, check) \ do { \ - auto _R = (result); \ - if (!(_R check)) { \ - fprintf(stderr, "Error from '%s' (%ld %s) in %s:%d.\n", \ - #result, (long int)_R, #check, __FILE__, __LINE__); \ - abort(); \ - } \ + auto _R = (result); \ + if (!(_R check)) { \ + fprintf(stderr, "Error from '%s' (%ld %s) in %s:%d.\n", \ + #result, (long int)_R, #check, __FILE__, __LINE__); \ + abort(); \ + } \ } while(0) #define CHECK_COND(result) \ do { \ - if (!(result)) { \ - fprintf(stderr, "Error from '%s' in %s:%d.\n", \ - #result, __FILE__, __LINE__); \ - abort(); \ - } \ + if (!(result)) { \ + fprintf(stderr, "Error from '%s' in %s:%d.\n", \ + #result, __FILE__, __LINE__); \ + abort(); \ + } \ } while(0) /**** END: http://svn.clifford.at/tools/trunk/examples/check.h ****/ diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h index cf6325570..c9ebd06c5 100644 --- a/passes/techmap/libparse.h +++ b/passes/techmap/libparse.h @@ -46,9 +46,17 @@ namespace Yosys LibertyAst *ast; LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {} ~LibertyParser() { if (ast) delete ast; } + + /* lexer return values: + 'v': identifier, string, array range [...] -> str holds the token string + 'n': newline + anything else is a single character. + */ int lexer(std::string &str); - LibertyAst *parse(); + + LibertyAst *parse(); void error(); + void error(const std::string &str); }; } diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore new file mode 100644 index 000000000..e6ec49c4a --- /dev/null +++ b/tests/liberty/.gitignore @@ -0,0 +1,2 @@ +*.log +test.ys diff --git a/tests/liberty/busdef.lib b/tests/liberty/busdef.lib new file mode 100644 index 000000000..b5e3d50b9 --- /dev/null +++ b/tests/liberty/busdef.lib @@ -0,0 +1,81 @@ +/********************************************/ +/* */ +/* Supergate cell library for Bench marking */ +/* */ +/* Symbiotic EDA GmbH / Moseley Instruments */ +/* Niels A. Moseley */ +/* */ +/* Process: none */ +/* */ +/* Date : 02-11-2018 */ +/* Version: 1.0 */ +/* */ +/********************************************/ + +library(supergate) { + technology (cmos); + revision : 1.0; + + time_unit : "1ps"; + pulling_resistance_unit : "1kohm"; + voltage_unit : "1V"; + current_unit : "1uA"; + + capacitive_load_unit(1,ff); + + default_inout_pin_cap : 7.0; + default_input_pin_cap : 7.0; + default_output_pin_cap : 0.0; + default_fanout_load : 1.0; + + default_wire_load_capacitance : 0.1; + default_wire_load_resistance : 1.0e-3; + default_wire_load_area : 0.0; + + nom_process : 1.0; + nom_temperature : 25.0; + nom_voltage : 1.2; + + delay_model : generic_cmos; + + type( IO_bus_3_to_0 ) { + base_type : array ; + data_type : bit ; + bit_width : 4; + bit_from : 3 ; + bit_to : 0 ; + downto : true ; + } + + cell (SRAM) { + area : 1 ; + memory() { + type : ram; + address_width : 4; + word_width : 4; + } + pin(CE1) { + direction : input; + capacitance : 0.021; + max_transition : 1.024; + switch_pin : true; + } + bus(I1) { + bus_type : IO_bus_3_to_0 ; + direction : input; + pin (I1[3:0]) { + timing() { + related_pin : "CE1" ; + timing_type : setup_rising ; + rise_constraint (scalar) { + values("0.0507786"); + } + fall_constraint (scalar) { + values("0.0507786"); + } + } + } + } + } + +} /* end */ diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib new file mode 100644 index 000000000..1474e2b59 --- /dev/null +++ b/tests/liberty/normal.lib @@ -0,0 +1,360 @@ +/********************************************/ +/* */ +/* Supergate cell library for Bench marking */ +/* */ +/* Symbiotic EDA GmbH / Moseley Instruments */ +/* Niels A. Moseley */ +/* */ +/* Process: none */ +/* */ +/* Date : 02-11-2018 */ +/* Version: 1.0 */ +/* */ +/********************************************/ + +library(supergate) { + technology (cmos); + revision : 1.0; + + time_unit : "1ps"; + pulling_resistance_unit : "1kohm"; + voltage_unit : "1V"; + current_unit : "1uA"; + + capacitive_load_unit(1,ff); + + default_inout_pin_cap : 7.0; + default_input_pin_cap : 7.0; + default_output_pin_cap : 0.0; + default_fanout_load : 1.0; + + default_wire_load_capacitance : 0.1; + default_wire_load_resistance : 1.0e-3; + default_wire_load_area : 0.0; + + nom_process : 1.0; + nom_temperature : 25.0; + nom_voltage : 1.2; + + delay_model : generic_cmos; + + /* Inverter */ + cell (inv) { + area : 1; + pin(A) { + direction : input; + } + + pin(Y) { + direction : output; + function : "A'"; + } + } + + /* tri-state inverter */ + cell (tri_inv) { + area : 4; + pin(A) { + direction : input; + } + pin(S) { + direction : input; + } + pin(Z) { + direction : output; + function : "A'"; + three_State : "S'"; + } + } + + cell (buffer) { + area : 5; + pin(A) { + direction : input; + } + pin(Y) { + direction : output; + function : "A"; + } + } + + /* 2-input NAND gate */ + cell (nand2) { + area : 3; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(Y) { + direction: output; + function : "(A * B)'"; + } + } + + /* 2-input NOR gate */ + cell (nor2) { + area : 3; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(Y) { + direction: output; + function : "(A + B)'"; + } + } + + /* 2-input XOR */ + cell (xor2) { + area : 6; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(Y) { + direction: output; + function : "(A *B') + (A' * B)"; + } + } + + /* 2-input inverting MUX */ + cell (imux2) { + area : 5; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(S) { + direction : input; + } + pin(Y) { + direction: output; + function : "( (A * S) + (B * S') )'"; + } + } + + /* D-type flip-flop with asynchronous reset and preset */ + cell (dff) + { + area : 6; + ff("IQ", "IQN") { + next_state : "D"; + clocked_on : "CLK"; + clear : "RESET"; + preset : "PRESET"; + clear_preset_var1 : L; + clear_preset_var2 : L; + } + pin(D) { + direction : input; + } + pin(CLK) { + direction : input; + } + pin(RESET) { + direction : input; + } + pin(PRESET) { + direction : input; + } + pin(Q) { + direction: output; + function : "IQ"; + timing() { + timing_type : rising_edge; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "CLK"; + } + timing () { + timing_type : clear; + timing_sense : positive_unate; + intrinsic_fall : 75; + related_pin : "RESET"; + } + timing () { + timing_type : preset; + timing_sense : negative_unate; + intrinsic_rise : 75; + related_pin : "PRESET"; + } + } + pin(QN) { + direction: output; + function : "IQN"; + timing() { + timing_type : rising_edge; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "CLK"; + } + timing () { + timing_type : preset; + timing_sense : negative_unate; + intrinsic_rise : 75; + related_pin : "RESET"; + } + timing () { + timing_type : clear; + timing_sense : positive_unate; + intrinsic_fall : 75; + related_pin : "PRESET"; + } + } + } + + /* Latch */ + cell(latch) { + area : 5; + latch ("IQ","IQN") { + enable : "G"; + data_in : "D"; + } + + pin(D) { + direction : input; + } + pin(G) { + direction : input; + } + + pin(Q) { + direction : output; + function : "IQ"; + internal_node : "Q"; + + timing() { + timing_type : rising_edge; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "G"; + } + + timing() { + timing_sense : positive_unate; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "D"; + } + } + + pin(QN) { + direction : output; + function : "IQN"; + internal_node : "QN"; + + timing() { + timing_type : rising_edge; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "G"; + } + + timing() { + timing_sense : negative_unate; + intrinsic_rise : 65; + intrinsic_fall : 65; + rise_resistance : 0; + fall_resistance : 0; + related_pin : "D"; + } + } + } + + /* 3 input AND-OR-INVERT gate */ + cell (aoi211) { + area : 3; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(C) { + direction : input; + } + pin(Y) { + direction: output; + function : "((A * B) + C)'"; + } + } + + + /* 3 input OR-AND-INVERT gate */ + cell (oai211) { + area : 3; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(C) { + direction : input; + } + pin(Y) { + direction: output; + function : "((A + B) * C)'"; + } + } + + /* half adder */ + cell (halfadder) { + area : 5; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(C) { + direction : output; + function : "(A * B)"; + } + pin(Y) { + direction: output; + function : "(A *B') + (A' * B)"; + } + } + + /* full adder */ + cell (fulladder) { + area : 8; + pin(A) { + direction : input; + } + pin(B) { + direction : input; + } + pin(CI) { + direction : input; + } + pin(CO) { + direction : output; + function : "(((A * B)+(B * CI))+(CI * A))"; + } + pin(Y) { + direction: output; + function : "((A^B)^CI)"; + } + } + +} /* end */ diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh new file mode 100755 index 000000000..7e2ed2370 --- /dev/null +++ b/tests/liberty/run-test.sh @@ -0,0 +1,10 @@ +#!/bin/bash +set -e + +for x in *.lib; do + echo "Running $x.." + echo "read_verilog small.v" > test.ys + echo "synth -top small" >> test.ys + echo "dfflibmap -liberty ${x}" >> test.ys + ../../yosys -ql ${x%.lib}.log -s test.ys +done diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib new file mode 100644 index 000000000..f7c20750a --- /dev/null +++ b/tests/liberty/semicolmissing.lib @@ -0,0 +1,72 @@ +/********************************************/ +/* */ +/* Supergate cell library for Bench marking */ +/* */ +/* Symbiotic EDA GmbH / Moseley Instruments */ +/* Niels A. Moseley */ +/* */ +/* Process: none */ +/* */ +/* Date : 24-03-2019 */ +/* Version: 1.0 */ +/* Version: 1.1 - Removed semicolons in */ +/* full adder */ +/* */ +/********************************************/ + +/* + semi colon is missing in full-adder specification + some TSMC liberty files are formatted this way.. +*/ + +library(supergate) { + technology (cmos); + revision : 1.0; + + time_unit : "1ps"; + pulling_resistance_unit : "1kohm"; + voltage_unit : "1V"; + current_unit : "1uA"; + + capacitive_load_unit(1,ff); + + default_inout_pin_cap : 7.0; + default_input_pin_cap : 7.0; + default_output_pin_cap : 0.0; + default_fanout_load : 1.0; + + default_wire_load_capacitance : 0.1; + default_wire_load_resistance : 1.0e-3; + default_wire_load_area : 0.0; + + nom_process : 1.0; + nom_temperature : 25.0; + nom_voltage : 1.2; + + delay_model : generic_cmos; + + /* full adder */ + cell (fulladder) { + area : 8 + pin(A) { + direction : input + } + pin(B) { + direction : input + } + pin(CI) { + direction : input + } + pin(CO) { + direction : output + function : "(((A * B)+(B * CI))+(CI * A))" + } + pin(Y) { + direction: output + function : "((A^B)^CI)" + } + } + +} /* end */ + + diff --git a/tests/liberty/small.v b/tests/liberty/small.v new file mode 100644 index 000000000..bd94be4fc --- /dev/null +++ b/tests/liberty/small.v @@ -0,0 +1,16 @@ +/** small, meaningless design to test loading of liberty files */ + +module small +( + input clk, + output reg[7:0] count +); + +initial count = 0; + +always @ (posedge clk) +begin + count <= count + 1'b1; +end + +endmodule