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Merge pull request #3985 from jix/static-elaboration-top

This commit is contained in:
Jannis Harder 2023-10-05 17:45:36 +02:00 committed by GitHub
parent 824fdaadf6 47a4b790f8
commit 6b8203f8a0
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 138 additions and 97 deletions
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55
frontends/verific/verific.cc
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@ -2495,15 +2495,20 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
for (const auto &i : parameters)
verific_params.Insert(i.first.c_str(), i.second.c_str());
if (top.empty()) {
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VerificExtensions::ElaborateAndRewrite("work", &verific_params);
verific_error_msg.clear();
#endif
if (top.empty()) {
netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &verific_params);
}
else {
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
#endif
{
Array veri_modules, vhdl_units;
if (veri_lib) {
@ -2524,6 +2529,10 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
}
}
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (!static_elaborate)
#endif
{
// Also elaborate all root modules since they may contain bind statements
MapIter mi;
FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
@ -2531,6 +2540,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
veri_modules.InsertLast(veri_module);
}
}
}
#ifdef VERIFIC_VHDL_SUPPORT
if (vhdl_lib) {
@ -2539,8 +2549,18 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
vhdl_units.InsertLast(vhdl_unit);
}
#endif
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) {
VerificExtensions::ElaborateAndRewrite("work", &veri_modules, &vhdl_units, &verific_params);
verific_error_msg.clear();
continue;
}
#endif
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &verific_params);
}
}
Netlist *nl;
int i;
@ -3595,6 +3615,9 @@ struct VerificPass : public Pass {
std::set<std::string> top_mod_names;
if (mode_all)
{
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
VerificExtensions::ElaborateAndRewrite(work, &parameters);
verific_error_msg.clear();
@ -3602,8 +3625,6 @@ struct VerificPass : public Pass {
if (!ppfile.empty())
veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
if (mode_all)
{
log("Running hier_tree::ElaborateAll().\n");
VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
@ -3628,15 +3649,22 @@ struct VerificPass : public Pass {
if (argidx == GetSize(args))
cmd_error(args, argidx, "No top module specified.\n");
Array *netlists = nullptr;
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
for (int static_elaborate = 1; static_elaborate >= 0; static_elaborate--)
#endif
{
VeriLibrary* veri_lib = veri_file::GetLibrary(work.c_str(), 1);
#ifdef VERIFIC_VHDL_SUPPORT
VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
#endif
Array veri_modules, vhdl_units;
for (; argidx < GetSize(args); argidx++)
for (int i = argidx; i < GetSize(args); i++)
{
const char *name = args[argidx].c_str();
const char *name = args[i].c_str();
top_mod_names.insert(name);
VeriModule *veri_module = veri_lib ? veri_lib->GetModule(name, 1) : nullptr;
@ -3677,7 +3705,18 @@ struct VerificPass : public Pass {
log_error("Can't find module/unit '%s'.\n", name);
}
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
if (static_elaborate) {
VerificExtensions::ElaborateAndRewrite(work, &veri_modules, &vhdl_units, &parameters);
verific_error_msg.clear();
#endif
if (!ppfile.empty())
veri_file::PrettyPrint(ppfile.c_str(), nullptr, work.c_str());
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
continue;
}
#endif
const char *lib_name = nullptr;
SetIter si;
FOREACH_SET_ITEM(veri_file::GetAllLOptions(), si, &lib_name) {
@ -3694,7 +3733,9 @@ struct VerificPass : public Pass {
}
log("Running hier_tree::Elaborate().\n");
Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
}
Netlist *nl;
int i;