riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Bugfix in RTLIL::SigSpec::remove2()

This commit is contained in:
Clifford Wolf 2016-12-31 16:14:42 +01:00
parent 7da7a6d1df
commit 6b2c23c721
1 changed files with 4 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
kernel/rtlil.cc
View File

@ -2766,10 +2766,11 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
other->unpack(); other->unpack();
} }
for (int i = GetSize(bits_) - 1; i >= 0; i--) { for (int i = GetSize(bits_) - 1; i >= 0; i--)
{
if (bits_[i].wire == NULL) continue; if (bits_[i].wire == NULL) continue;
for (auto &pattern_chunk : pattern.chunks()) { for (auto &pattern_chunk : pattern.chunks())
if (bits_[i].wire == pattern_chunk.wire && if (bits_[i].wire == pattern_chunk.wire &&
bits_[i].offset >= pattern_chunk.offset && bits_[i].offset >= pattern_chunk.offset &&
bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) { bits_[i].offset < pattern_chunk.offset + pattern_chunk.width) {
@ -2779,7 +2780,7 @@ void RTLIL::SigSpec::remove2(const RTLIL::SigSpec &pattern, RTLIL::SigSpec *othe
other->bits_.erase(other->bits_.begin() + i); other->bits_.erase(other->bits_.begin() + i);
other->width_--; other->width_--;
} }
} break;
} }
} }