mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/peepopt_dffmuxext' into xc7dsp
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commit
6b23c7c227
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@ -50,8 +50,9 @@ code
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if (GetSize(const_factor_cnst) > 20)
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if (GetSize(const_factor_cnst) > 20)
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reject;
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reject;
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if (GetSize(port(shift, \Y)) > const_factor)
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if (shift->type.in($shift, $shiftx))
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reject;
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if (GetSize(port(shift, \Y)) > const_factor)
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reject;
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int factor_bits = ceil_log2(const_factor);
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int factor_bits = ceil_log2(const_factor);
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SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
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SigSpec mul_din = port(mul, const_factor_port == \A ? \B : \A);
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@ -5,7 +5,7 @@ endmodule
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EOT
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EOT
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prep -nokeepdc
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prep -nokeepdc
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equiv_opt peepopt
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equiv_opt -assert peepopt
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design -load postopt
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design -load postopt
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clean
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clean
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select -assert-count 1 t:$shiftx
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select -assert-count 1 t:$shiftx
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@ -16,16 +16,16 @@ select -assert-count 0 t:$shiftx t:* %D
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design -reset
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design -reset
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read_verilog <<EOT
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read_verilog <<EOT
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module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
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module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
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assign y = 1'b1 >> (w * (3'b110));
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assign y = 1'b1 >> (w * (8'b110));
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endmodule
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endmodule
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EOT
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EOT
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prep -nokeepdc
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prep -nokeepdc
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equiv_opt peepopt
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equiv_opt -assert peepopt
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design -load postopt
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design -load postopt
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clean
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clean
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$mul
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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####################
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####################
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@ -40,7 +40,7 @@ endmodule
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EOT
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EOT
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prep -nokeepdc
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prep -nokeepdc
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equiv_opt peepopt
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equiv_opt -assert peepopt
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design -load postopt
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design -load postopt
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clean
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clean
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select -assert-count 0 t:*
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select -assert-count 0 t:*
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@ -55,7 +55,7 @@ endmodule
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EOT
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EOT
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prep -nokeepdc
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prep -nokeepdc
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equiv_opt peepopt
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equiv_opt -assert peepopt
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design -load postopt
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design -load postopt
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clean
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clean
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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