riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Remove unused variable

This commit is contained in:
Eddie Hung 2019-08-16 13:35:39 -07:00
parent 49301b733e
commit 6b156beda1
1 changed files with 0 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
frontends/aiger/aigerparse.cc
View File

@ -901,11 +901,6 @@ void AigerReader::post_process()
RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
if (cell) { // ABC could have optimised this box away
module->rename(cell, escaped_s);
#ifndef NDEBUG
RTLIL::Module* box_module = design->module(cell->type);
log_assert(box_module);
#endif
for (const auto &i : cell->connections()) {
RTLIL::IdString port_name = i.first;
RTLIL::SigSpec rhs = i.second;