mirror of https://github.com/YosysHQ/yosys.git
Remove unused variable
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@ -901,11 +901,6 @@ void AigerReader::post_process()
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RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
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RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
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if (cell) { // ABC could have optimised this box away
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if (cell) { // ABC could have optimised this box away
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module->rename(cell, escaped_s);
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module->rename(cell, escaped_s);
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#ifndef NDEBUG
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RTLIL::Module* box_module = design->module(cell->type);
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log_assert(box_module);
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#endif
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for (const auto &i : cell->connections()) {
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for (const auto &i : cell->connections()) {
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RTLIL::IdString port_name = i.first;
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RTLIL::IdString port_name = i.first;
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RTLIL::SigSpec rhs = i.second;
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RTLIL::SigSpec rhs = i.second;
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