mirror of https://github.com/YosysHQ/yosys.git
Use `log_push()` and `log_pop()` and show the satisfiable model when `-specialize` is not specified.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
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@ -178,6 +178,29 @@ void specialize(RTLIL::Module *module, const QbfSolutionType &sol) {
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}
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}
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}
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}
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void dump_model(RTLIL::Module *module, const QbfSolutionType &sol) {
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log("Satisfiable model:\n");
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std::map<std::string, std::string> hole_loc_to_name = get_hole_loc_name_map(module, sol);
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for (auto &it : sol.hole_to_value) {
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std::string hole_loc = it.first;
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std::string hole_value = it.second;
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#ifndef NDEBUG
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auto pos = hole_loc_to_name.find(hole_loc);
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log_assert(pos != hole_loc_to_name.end());
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#endif
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std::string hole_name = hole_loc_to_name[hole_loc];
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log("\t%s = %lu'b%s\n", hole_name.c_str(), hole_value.size(), hole_value.c_str());
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std::vector<RTLIL::SigBit> value_bv;
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value_bv.reserve(hole_value.size());
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for (char c : hole_value)
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value_bv.push_back(c == '1'? RTLIL::S1 : RTLIL::S0);
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std::reverse(value_bv.begin(), value_bv.end());
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}
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}
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void allconstify_inputs(RTLIL::Module *module, const std::set<std::string> &input_wires) {
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void allconstify_inputs(RTLIL::Module *module, const std::set<std::string> &input_wires) {
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for (auto &n : input_wires) {
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for (auto &n : input_wires) {
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RTLIL::Wire *input = module->wire(n);
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RTLIL::Wire *input = module->wire(n);
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@ -242,6 +265,7 @@ QbfSolutionType qbf_solve(RTLIL::Module *mod, const QbfSolveOptions &opt) {
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log_assert(mod->design != nullptr);
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log_assert(mod->design != nullptr);
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#endif
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#endif
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Pass::call(mod->design, smt2_command);
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Pass::call(mod->design, smt2_command);
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log_header(mod->design, "Solving QBF-SAT problem.\n");
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//Execute and capture stdout from `yosys-smtbmc -s z3 -t 1 -g --binary [--dump-smt2 <file>]`
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//Execute and capture stdout from `yosys-smtbmc -s z3 -t 1 -g --binary [--dump-smt2 <file>]`
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{
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{
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@ -445,6 +469,7 @@ struct QbfSatPass : public Pass {
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if (module == NULL)
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if (module == NULL)
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log_cmd_error("Can't perform QBF-SAT on an empty selection!\n");
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log_cmd_error("Can't perform QBF-SAT on an empty selection!\n");
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log_push();
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if (!opt.specialize_from_file) {
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if (!opt.specialize_from_file) {
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//Save the design to restore after modiyfing the current module.
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//Save the design to restore after modiyfing the current module.
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std::string module_name = module->name.str();
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std::string module_name = module->name.str();
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@ -474,6 +499,8 @@ struct QbfSatPass : public Pass {
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if (opt.specialize) {
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if (opt.specialize) {
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specialize(module, ret);
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specialize(module, ret);
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Pass::call(design, "opt_clean");
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Pass::call(design, "opt_clean");
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} else {
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dump_model(module, ret);
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}
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}
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if (opt.unsat)
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if (opt.unsat)
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log_cmd_error("expected problem to be UNSAT\n");
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log_cmd_error("expected problem to be UNSAT\n");
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@ -484,6 +511,7 @@ struct QbfSatPass : public Pass {
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specialize_from_file(module, opt.specialize_soln_file);
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specialize_from_file(module, opt.specialize_soln_file);
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Pass::call(design, "opt_clean");
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Pass::call(design, "opt_clean");
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}
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}
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log_pop();
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}
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}
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} QbfSatPass;
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} QbfSatPass;
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