mirror of https://github.com/YosysHQ/yosys.git
sim: Change clocked read port suggestion to `memory_nordff`
`memory_nordff` has the advantage that it can be called just ahead of the simulation step no matter whether the clocked read port has been inferred or was explicitly instantiated in a flow.
This commit is contained in:
parent
6b8203f8a0
commit
6ac43e49bc
|
@ -579,7 +579,7 @@ struct SimInstance
|
|||
Const data = Const(State::Sx, mem.width << port.wide_log2);
|
||||
|
||||
if (port.clk_enable)
|
||||
log_error("Memory %s.%s has clocked read ports. Run 'memory' with -nordff.\n", log_id(module), log_id(mem.memid));
|
||||
log_error("Memory %s.%s has clocked read ports. Run 'memory_nordff' to transform the circuit to remove those.\n", log_id(module), log_id(mem.memid));
|
||||
|
||||
if (addr.is_fully_def()) {
|
||||
int addr_int = addr.as_int();
|
||||
|
|
Loading…
Reference in New Issue