mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'upstream/master'
This commit is contained in:
commit
6a809a1bb1
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@ -34,3 +34,4 @@
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/libyosys.so
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/libyosys.so
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/tests/unit/bintest/
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/tests/unit/bintest/
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/tests/unit/objtest/
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/tests/unit/objtest/
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/tests/ystests
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@ -64,7 +64,7 @@ if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
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brew tap Homebrew/bundle
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brew tap Homebrew/bundle
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brew bundle
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brew bundle
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brew install ccache
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brew install ccache
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brew install gcc
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brew install gcc@7
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echo
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echo
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echo -en 'travis_fold:end:before_install.brew\\r'
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echo -en 'travis_fold:end:before_install.brew\\r'
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echo
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echo
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@ -373,6 +373,7 @@ Finally run all tests with "make config-{clang,gcc,gcc-4.8}":
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cd ~yosys
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cd ~yosys
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make clean
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make clean
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make test
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make test
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make ystests
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make vloghtb
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make vloghtb
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make install
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make install
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8
Makefile
8
Makefile
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@ -585,6 +585,14 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS)
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@echo " Passed \"make vloghtb\"."
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@echo " Passed \"make vloghtb\"."
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@echo ""
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@echo ""
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ystests: $(TARGETS) $(EXTRA_TARGETS)
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rm -rf tests/ystests
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git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests
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+PATH="$$PWD:$$PATH" cd tests/ystests && $(MAKE)
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@echo ""
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@echo " Finished \"make ystests\"."
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@echo ""
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# Unit test
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# Unit test
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unit-test: libyosys.so
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unit-test: libyosys.so
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@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \
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@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \
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@ -779,6 +779,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
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return true;
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return true;
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}
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}
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if (cell->type == "$lut")
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{
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f << stringf("%s" "assign ", indent.c_str());
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dump_sigspec(f, cell->getPort("\\Y"));
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f << stringf(" = ");
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dump_const(f, cell->parameters.at("\\LUT"));
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f << stringf(" >> ");
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dump_attributes(f, "", cell->attributes, ' ');
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dump_sigspec(f, cell->getPort("\\A"));
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f << stringf(";\n");
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return true;
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}
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if (cell->type == "$dffsr")
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if (cell->type == "$dffsr")
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{
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{
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SigSpec sig_clk = cell->getPort("\\CLK");
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SigSpec sig_clk = cell->getPort("\\CLK");
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@ -64,6 +64,7 @@ YOSYS_NAMESPACE_BEGIN
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int verific_verbose;
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int verific_verbose;
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bool verific_import_pending;
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bool verific_import_pending;
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string verific_error_msg;
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string verific_error_msg;
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int verific_sva_fsm_limit;
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vector<string> verific_incdirs, verific_libdirs;
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vector<string> verific_incdirs, verific_libdirs;
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@ -1618,6 +1619,8 @@ struct VerificExtNets
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void verific_import(Design *design, std::string top)
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void verific_import(Design *design, std::string top)
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{
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{
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verific_sva_fsm_limit = 16;
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std::set<Netlist*> nl_todo, nl_done;
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std::set<Netlist*> nl_todo, nl_done;
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{
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{
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@ -1789,6 +1792,9 @@ struct VerificPass : public Pass {
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log(" -nosva\n");
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log(" -nosva\n");
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log(" Ignore SVA properties, do not infer checker logic.\n");
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log(" Ignore SVA properties, do not infer checker logic.\n");
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log("\n");
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log("\n");
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log(" -L <int>\n");
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log(" Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
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log("\n");
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log(" -n\n");
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log(" -n\n");
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log(" Keep all Verific names on instances and nets. By default only\n");
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log(" Keep all Verific names on instances and nets. By default only\n");
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log(" user-declared names are preserved.\n");
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log(" user-declared names are preserved.\n");
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@ -1830,6 +1836,7 @@ struct VerificPass : public Pass {
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}
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}
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verific_verbose = 0;
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verific_verbose = 0;
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verific_sva_fsm_limit = 16;
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const char *release_str = Message::ReleaseString();
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const char *release_str = Message::ReleaseString();
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time_t release_time = Message::ReleaseDate();
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time_t release_time = Message::ReleaseDate();
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@ -2036,6 +2043,10 @@ struct VerificPass : public Pass {
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mode_nosva = true;
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mode_nosva = true;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
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verific_sva_fsm_limit = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-n") {
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if (args[argidx] == "-n") {
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mode_names = true;
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mode_names = true;
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continue;
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continue;
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@ -101,6 +101,8 @@ void verific_import_sva_cover(VerificImporter *importer, Verific::Instance *inst
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void verific_import_sva_trigger(VerificImporter *importer, Verific::Instance *inst);
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void verific_import_sva_trigger(VerificImporter *importer, Verific::Instance *inst);
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bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net);
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bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net);
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extern int verific_sva_fsm_limit;
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YOSYS_NAMESPACE_END
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YOSYS_NAMESPACE_END
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#endif
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#endif
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@ -466,13 +466,14 @@ struct SvaFsm
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dnode.ctrl.sort_and_unify();
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dnode.ctrl.sort_and_unify();
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if (GetSize(dnode.ctrl) > 16) {
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if (GetSize(dnode.ctrl) > verific_sva_fsm_limit) {
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if (verific_verbose >= 2) {
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if (verific_verbose >= 2) {
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log(" detected state explosion in DFSM generation:\n");
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log(" detected state explosion in DFSM generation:\n");
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dump();
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dump();
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log(" ctrl signal: %s\n", log_signal(dnode.ctrl));
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log(" ctrl signal: %s\n", log_signal(dnode.ctrl));
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}
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}
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log_error("SVA DFSM state ctrl signal has %d (>16) bits. Stopping to prevent exponential design size explosion.\n", GetSize(dnode.ctrl));
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log_error("SVA DFSM state ctrl signal has %d (>%d) bits. Stopping to prevent exponential design size explosion.\n",
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GetSize(dnode.ctrl), verific_sva_fsm_limit);
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}
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}
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for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++)
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for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++)
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@ -162,7 +162,6 @@ struct SetundefPass : public Pass {
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continue;
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continue;
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}
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}
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if (args[argidx] == "-expose") {
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if (args[argidx] == "-expose") {
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got_value = true;
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expose_mode = true;
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expose_mode = true;
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continue;
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continue;
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}
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}
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@ -212,6 +211,13 @@ struct SetundefPass : public Pass {
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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if (!got_value && expose_mode) {
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log("Using default as -undef with -expose.\n");
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got_value = true;
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worker.next_bit_mode = MODE_UNDEF;
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worker.next_bit_state = 0;
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}
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if (expose_mode && !undriven_mode)
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if (expose_mode && !undriven_mode)
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log_cmd_error("Option -expose must be used with option -undriven.\n");
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log_cmd_error("Option -expose must be used with option -undriven.\n");
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if (!got_value)
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if (!got_value)
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@ -778,7 +778,7 @@ struct SimPass : public Pass {
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log(" number of cycles to simulate (default: 20)\n");
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log(" number of cycles to simulate (default: 20)\n");
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log("\n");
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log("\n");
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log(" -a\n");
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log(" -a\n");
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log(" include all nets in VCD output, nut just those with public names\n");
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log(" include all nets in VCD output, not just those with public names\n");
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log("\n");
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log("\n");
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log(" -w\n");
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log(" -w\n");
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log(" writeback mode: use final simulation state as new init state\n");
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log(" writeback mode: use final simulation state as new init state\n");
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@ -920,19 +920,40 @@ parameter A_SIGNED = 1'b0;
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parameter B_SIGNED = 1'b0;
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parameter B_SIGNED = 1'b0;
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endmodule
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endmodule
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(* blackbox *)
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module SB_SPRAM256KA (
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module SB_SPRAM256KA (
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input [13:0] ADDRESS,
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input [13:0] ADDRESS,
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input [15:0] DATAIN,
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input [15:0] DATAIN,
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input [3:0] MASKWREN,
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input [3:0] MASKWREN,
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input WREN,
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input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
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input CHIPSELECT,
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output reg [15:0] DATAOUT
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input CLOCK,
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input STANDBY,
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input SLEEP,
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input POWEROFF,
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output [15:0] DATAOUT
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);
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);
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`ifndef BLACKBOX
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reg [15:0] mem [0:16383];
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wire off = SLEEP || !POWEROFF;
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integer i;
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always @(negedge POWEROFF) begin
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for (i = 0; i <= 16383; i = i+1)
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mem[i] = 'bx;
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end
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always @(posedge CLOCK, posedge off) begin
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if (off) begin
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DATAOUT <= 0;
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end else
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if (CHIPSELECT && !STANDBY && !WREN) begin
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DATAOUT <= mem[ADDRESS];
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end else begin
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if (CHIPSELECT && !STANDBY && WREN) begin
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if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
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if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
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if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
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if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
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end
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DATAOUT <= 'bx;
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end
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end
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`endif
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endmodule
|
endmodule
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|
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||||||
(* blackbox *)
|
(* blackbox *)
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||||||
|
|
Loading…
Reference in New Issue