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Copy Verific vdbs files to Yosys "share" data directory

This commit is contained in:
Clifford Wolf 2014-03-13 17:34:31 +01:00
parent 34e54cda5b
commit 6a53bc7b27
3 changed files with 24 additions and 9 deletions
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2
Makefile
View File

@ -92,7 +92,7 @@ endif
ifeq ($(ENABLE_VERIFIC),1) ifeq ($(ENABLE_VERIFIC),1)
VERIFIC_DIR ?= /usr/local/src/verific_lib_eval VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
VERIFIC_COMPONENTS ?= verilog vhdl database util containers VERIFIC_COMPONENTS ?= verilog vhdl database util containers
CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -D'VERIFIC_DIR="$(VERIFIC_DIR)"' CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS))
endif endif

15
frontends/verific/Makefile.inc
View File

@ -1 +1,16 @@
OBJS += frontends/verific/verific.o OBJS += frontends/verific/verific.o
ifeq ($(ENABLE_VERIFIC),1)
EXTRA_TARGETS += share/verific
share/verific:
rm -rf share/verific.new
mkdir -p share/verific.new
cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs share/verific.new/vhdl_vdbs_1993
cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008 share/verific.new/vhdl_vdbs_2008
mv share/verific.new share/verific
endif

16
frontends/verific/verific.cc
View File

@ -27,7 +27,7 @@
#include <string.h> #include <string.h>
#include <dirent.h> #include <dirent.h>
#ifdef VERIFIC_DIR #ifdef YOSYS_ENABLE_VERIFIC
#include "veri_file.h" #include "veri_file.h"
#include "vhdl_file.h" #include "vhdl_file.h"
@ -482,7 +482,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
} }
} }
#endif /* VERIFIC_DIR */ #endif /* YOSYS_ENABLE_VERIFIC */
struct VerificPass : public Pass { struct VerificPass : public Pass {
VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
@ -509,7 +509,7 @@ struct VerificPass : public Pass {
log("Visit http://verific.com/ for more information on Verific.\n"); log("Visit http://verific.com/ for more information on Verific.\n");
log("\n"); log("\n");
} }
#ifdef VERIFIC_DIR #ifdef YOSYS_ENABLE_VERIFIC
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
log_header("Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n"); log_header("Executing VERIFIC (loading Verilog and VHDL designs using Verific).\n");
@ -553,7 +553,7 @@ struct VerificPass : public Pass {
} }
if (args.size() > 1 && args[1] == "-vhdl87") { if (args.size() > 1 && args[1] == "-vhdl87") {
vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs"); vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
for (size_t argidx = 2; argidx < args.size(); argidx++) for (size_t argidx = 2; argidx < args.size(); argidx++)
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87)) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87))
log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str()); log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
@ -561,7 +561,7 @@ struct VerificPass : public Pass {
} }
if (args.size() > 1 && args[1] == "-vhdl93") { if (args.size() > 1 && args[1] == "-vhdl93") {
vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs"); vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
for (size_t argidx = 2; argidx < args.size(); argidx++) for (size_t argidx = 2; argidx < args.size(); argidx++)
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93)) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93))
log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str()); log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
@ -569,7 +569,7 @@ struct VerificPass : public Pass {
} }
if (args.size() > 1 && args[1] == "-vhdl2k") { if (args.size() > 1 && args[1] == "-vhdl2k") {
vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs"); vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
for (size_t argidx = 2; argidx < args.size(); argidx++) for (size_t argidx = 2; argidx < args.size(); argidx++)
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K)) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K))
log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str()); log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
@ -577,7 +577,7 @@ struct VerificPass : public Pass {
} }
if (args.size() > 1 && args[1] == "-vhdl2008") { if (args.size() > 1 && args[1] == "-vhdl2008") {
vhdl_file::SetDefaultLibraryPath(VERIFIC_DIR "/vhdl_packages/vdbs"); vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
for (size_t argidx = 2; argidx < args.size(); argidx++) for (size_t argidx = 2; argidx < args.size(); argidx++)
if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008)) if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008))
log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str()); log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
@ -617,7 +617,7 @@ struct VerificPass : public Pass {
log_cmd_error("Missing or unsupported mode parameter.\n"); log_cmd_error("Missing or unsupported mode parameter.\n");
} }
#else /* VERIFIC_DIR */ #else /* YOSYS_ENABLE_VERIFIC */
virtual void execute(std::vector<std::string>, RTLIL::Design *) { virtual void execute(std::vector<std::string>, RTLIL::Design *) {
log_cmd_error("This version of Yosys is built without Verific support.\n"); log_cmd_error("This version of Yosys is built without Verific support.\n");
} }