mirror of https://github.com/YosysHQ/yosys.git
booth: Clean unused FA index variable
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@ -1046,7 +1046,6 @@ struct BoothPassWorker {
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//
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// sum up the partial products
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//
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int fa_el_ix = 0;
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int fa_row_ix = 0;
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std::vector<SigSpec> fa_sum;
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std::vector<SigSpec> fa_carry;
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@ -1074,7 +1073,7 @@ struct BoothPassWorker {
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// special because these are driven by a decoder and prior fa.
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for (fa_row_ix = 1; fa_row_ix < fa_row_count; fa_row_ix++) {
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// end two bits: sign extension
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SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_%d_L", fa_row_ix, fa_el_ix)),
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SigBit d_inv = module->NotGate(NEW_ID_SUFFIX(stringf("bfa_se_inv_%d_L", fa_row_ix)),
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PPij[((fa_row_ix + 1) * dec_count) + dec_count - 1]);
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BuildBitwiseFa(module, NEW_ID_SUFFIX(stringf("fa_row_%d", fa_row_ix)).str(),
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