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presentation progress

This commit is contained in:
Clifford Wolf 2014-02-02 17:57:14 +01:00
parent aa732b0c73
commit 6983d3f10b
10 changed files with 80 additions and 0 deletions
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32
manual/PRESENTATION_ExSyn.tex
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@ -101,7 +101,39 @@ proc_clean # if all went fine, this should remove all the processes
Many commands can not operate on modules with ``processes'' in them. Usually
a call to {\tt proc} is the first command in the actual synthesis procedure
after design elaboration.
\end{frame}
\begin{frame}[fragile]{\subsecname{} -- Example 1/TBD}
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_00.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_00.ys}
\end{columns}
% \includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_00.pdf}
\hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_00.pdf}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 2/TBD}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]{PRESENTATION_ExSyn/proc_01.pdf}}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_01.v}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_01.ys}
\end{columns}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 3/TBD}
\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]{PRESENTATION_ExSyn/proc_02.pdf}}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_02.ys}
\column[t]{5cm}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_02.v}
\end{columns}
\end{frame}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

1
manual/PRESENTATION_ExSyn/.gitignore vendored Normal file
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@ -0,0 +1 @@
*.dot

12
manual/PRESENTATION_ExSyn/Makefile Normal file
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@ -0,0 +1,12 @@
all: proc_00.pdf proc_01.pdf proc_02.pdf
proc_00.pdf: proc_00.v proc_00.ys
../../yosys -p 'script proc_00.ys; show -notitle -prefix proc_00 -format pdf'
proc_01.pdf: proc_01.v proc_01.ys
../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf'
proc_02.pdf: proc_02.v proc_02.ys
../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf'

7
manual/PRESENTATION_ExSyn/proc_00.v Normal file
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@ -0,0 +1,7 @@
module test(input D, C, R, output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= 0;
else
Q <= D;
endmodule

3
manual/PRESENTATION_ExSyn/proc_00.ys Normal file
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@ -0,0 +1,3 @@
read_verilog proc_00.v
hierarchy -check -top test
proc;;

8
manual/PRESENTATION_ExSyn/proc_01.v Normal file
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@ -0,0 +1,8 @@
module test(input D, C, R, RV,
output reg Q);
always @(posedge C, posedge R)
if (R)
Q <= RV;
else
Q <= D;
endmodule

3
manual/PRESENTATION_ExSyn/proc_01.ys Normal file
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@ -0,0 +1,3 @@
read_verilog proc_01.v
hierarchy -check -top test
proc;;

10
manual/PRESENTATION_ExSyn/proc_02.v Normal file
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@ -0,0 +1,10 @@
module test(input A, B, C, D, E,
output reg Y);
always @* begin
Y <= A;
if (B)
Y <= C;
if (D)
Y <= E;
end
endmodule

3
manual/PRESENTATION_ExSyn/proc_02.ys Normal file
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@ -0,0 +1,3 @@
read_verilog proc_02.v
hierarchy -check -top test
proc;;

1
manual/presentation.sh
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@ -27,6 +27,7 @@ PDFTEX_OPT="-shell-escape -halt-on-error"
if ! $fast_mode; then
md5sum *.aux *.snm *.nav *.toc > autoloop.old
make -C PRESENTATION_Intro
make -C PRESENTATION_ExSyn
fi
set -ex