mirror of https://github.com/YosysHQ/yosys.git
Fix spacing again, A_forward -> A_backward
This commit is contained in:
parent
11886c874c
commit
694d40719f
|
@ -37,49 +37,51 @@ module \$shiftx (A, B, Y);
|
||||||
generate
|
generate
|
||||||
genvar i;
|
genvar i;
|
||||||
wire [A_WIDTH-1:0] A_forward;
|
wire [A_WIDTH-1:0] A_forward;
|
||||||
assign A_forward[A_WIDTH-1] = A[A_WIDTH-1];
|
assign A_backward[A_WIDTH-1] = A[A_WIDTH-1];
|
||||||
for (i = A_WIDTH-2; i >= 0; i = i - 1)
|
for (i = A_WIDTH-2; i >= 0; i = i - 1)
|
||||||
if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
|
if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
|
||||||
assign A_forward[i] = A_forward[i+1];
|
assign A_backward[i] = A_backward[i+1];
|
||||||
else
|
else
|
||||||
assign A_forward[i] = A[i];
|
assign A_backward[i] = A[i];
|
||||||
|
|
||||||
wire [A_WIDTH-1:0] A_without_x;
|
wire [A_WIDTH-1:0] A_without_x;
|
||||||
assign A_without_x[0] = A_forward[0];
|
assign A_without_x[0] = A_backward[0];
|
||||||
for (i = 1; i < A_WIDTH; i = i + 1)
|
for (i = 1; i < A_WIDTH; i = i + 1)
|
||||||
if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
|
if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'bx)
|
||||||
assign A_without_x[i] = A_without_x[i-1];
|
assign A_without_x[i] = A_without_x[i-1];
|
||||||
else
|
else
|
||||||
assign A_without_x[i] = A[i];
|
assign A_without_x[i] = A[i];
|
||||||
|
|
||||||
if (B_SIGNED) begin
|
if (B_SIGNED) begin
|
||||||
if (B_WIDTH < 4 || A_WIDTH <= 4)
|
if (B_WIDTH < 4 || A_WIDTH <= 4)
|
||||||
wire _TECHMAP_FAIL_ = 1;
|
wire _TECHMAP_FAIL_ = 1;
|
||||||
else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
|
else if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
|
||||||
// Optimisation to remove B_SIGNED if sign bit of B is constant-0
|
// Optimisation to remove B_SIGNED if sign bit of B is constant-0
|
||||||
\$__XILINX_SHIFTX #(
|
\$__XILINX_SHIFTX #(
|
||||||
.A_SIGNED(A_SIGNED),
|
.A_SIGNED(A_SIGNED),
|
||||||
.B_SIGNED(0),
|
.B_SIGNED(0),
|
||||||
.A_WIDTH(A_WIDTH),
|
.A_WIDTH(A_WIDTH),
|
||||||
.B_WIDTH(B_WIDTH-1'd1),
|
.B_WIDTH(B_WIDTH-1'd1),
|
||||||
.Y_WIDTH(Y_WIDTH)
|
.Y_WIDTH(Y_WIDTH)
|
||||||
) _TECHMAP_REPLACE_ (
|
) _TECHMAP_REPLACE_ (
|
||||||
.A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
|
.A(A_without_x), .B(B[B_WIDTH-2:0]), .Y(Y)
|
||||||
);
|
);
|
||||||
end
|
else
|
||||||
else begin
|
wire _TECHMAP_FAIL_ = 1;
|
||||||
if (B_WIDTH < 3 || A_WIDTH <= 4)
|
end
|
||||||
wire _TECHMAP_FAIL_ = 1;
|
else begin
|
||||||
else
|
if (B_WIDTH < 3 || A_WIDTH <= 4)
|
||||||
\$__XILINX_SHIFTX #(
|
wire _TECHMAP_FAIL_ = 1;
|
||||||
.A_SIGNED(A_SIGNED),
|
else
|
||||||
.B_SIGNED(B_SIGNED),
|
\$__XILINX_SHIFTX #(
|
||||||
.A_WIDTH(A_WIDTH),
|
.A_SIGNED(A_SIGNED),
|
||||||
.B_WIDTH(B_WIDTH),
|
.B_SIGNED(B_SIGNED),
|
||||||
.Y_WIDTH(Y_WIDTH)
|
.A_WIDTH(A_WIDTH),
|
||||||
) _TECHMAP_REPLACE_ (
|
.B_WIDTH(B_WIDTH),
|
||||||
.A(A_without_x), .B(B), .Y(Y)
|
.Y_WIDTH(Y_WIDTH)
|
||||||
);
|
) _TECHMAP_REPLACE_ (
|
||||||
|
.A(A_without_x), .B(B), .Y(Y)
|
||||||
|
);
|
||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
endmodule
|
endmodule
|
||||||
|
|
Loading…
Reference in New Issue