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Update README.md from master

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Eddie Hung 2019-05-28 09:32:18 -07:00
parent ba9513b325
commit 6931a3a47d
1 changed files with 3 additions and 3 deletions
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@ -366,7 +366,7 @@ Verilog Attributes and non-standard features
- When defining a macro with `define, all text between triple double quotes - When defining a macro with `define, all text between triple double quotes
is interpreted as macro body, even if it contains unescaped newlines. The is interpreted as macro body, even if it contains unescaped newlines. The
tipple double quotes are removed from the macro body. For example: triple double quotes are removed from the macro body. For example:
`define MY_MACRO(a, b) """ `define MY_MACRO(a, b) """
assign a = 23; assign a = 23;
@ -459,7 +459,7 @@ Non-standard or SystemVerilog features for formal verification
supported in any clocked block. supported in any clocked block.
- The syntax ``@($global_clock)`` can be used to create FFs that have no - The syntax ``@($global_clock)`` can be used to create FFs that have no
explicit clock input ($ff cells). The same can be achieved by using explicit clock input (``$ff`` cells). The same can be achieved by using
``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>`` ``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
is marked with the ``(* gclk *)`` Verilog attribute. is marked with the ``(* gclk *)`` Verilog attribute.
@ -472,7 +472,7 @@ from SystemVerilog:
- The ``assert`` statement from SystemVerilog is supported in its most basic - The ``assert`` statement from SystemVerilog is supported in its most basic
form. In module context: ``assert property (<expression>);`` and within an form. In module context: ``assert property (<expression>);`` and within an
always block: ``assert(<expression>);``. It is transformed to a $assert cell. always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
- The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
also supported. The same limitations as with the ``assert`` statement apply. also supported. The same limitations as with the ``assert`` statement apply.