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Merge pull request #1346 from mmicko/fix_ecp5_cells_sim 

Fix TRELLIS_FF simulation model
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David Shah 2019-09-01 10:01:27 +01:00 committed by GitHub
parent 90b44113d8 a3c16a0565
commit 68fe1eba6c
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1 changed files with 7 additions and 6 deletions
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techlibs/ecp5/cells_sim.v
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@ -229,14 +229,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
parameter REGSET = "RESET"; parameter REGSET = "RESET";
parameter [127:0] LSRMODE = "LSR"; parameter [127:0] LSRMODE = "LSR";
reg muxce; wire muxce;
always @(*) generate
case (CEMUX) case (CEMUX)
"1": muxce = 1'b1; "1": assign muxce = 1'b1;
"0": muxce = 1'b0; "0": assign muxce = 1'b0;
"INV": muxce = ~CE; "INV": assign muxce = ~CE;
default: muxce = CE; default: assign muxce = CE;
endcase endcase
endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR; wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK; wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;