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Add NX_DFR simulation model

This commit is contained in:
Miodrag Milanovic 2024-07-04 07:41:55 +02:00
parent eb30be6189
commit 6876a27547
2 changed files with 50 additions and 19 deletions
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38
techlibs/nanoxplore/cells_bb.v
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@ -57,25 +57,25 @@
// output O; // output O;
//endmodule //endmodule
(* blackbox *) // (* blackbox *)
module NX_DFR(I, CK, L, R, O); // module NX_DFR(I, CK, L, R, O);
input CK; // input CK;
input I; // input I;
input L; // input L;
output O; // output O;
input R; // input R;
parameter data_inv = 1'b0; // parameter data_inv = 1'b0;
parameter dff_edge = 1'b0; // parameter dff_edge = 1'b0;
parameter dff_init = 1'b0; // parameter dff_init = 1'b0;
parameter dff_load = 1'b0; // parameter dff_load = 1'b0;
parameter dff_sync = 1'b0; // parameter dff_sync = 1'b0;
parameter dff_type = 1'b0; // parameter dff_type = 1'b0;
parameter iobname = ""; // parameter iobname = "";
parameter location = ""; // parameter location = "";
parameter mode = 0; // parameter mode = 0;
parameter path = 0; // parameter path = 0;
parameter ring = 0; // parameter ring = 0;
endmodule // endmodule
// Special mode of NX_DFR // Special mode of NX_DFR
//(* blackbox *) //(* blackbox *)

31
techlibs/nanoxplore/cells_sim.v
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@ -36,6 +36,37 @@ always @(posedge clock, posedge async_reset)
endmodule endmodule
(* abc9_box, lib_whitebox *)
module NX_DFR(input I, CK, L, R, output O);
parameter data_inv = 1'b0;
parameter dff_edge = 1'b0;
parameter dff_init = 1'b0;
parameter dff_load = 1'b0;
parameter dff_sync = 1'b0;
parameter dff_type = 1'b0;
parameter iobname = "";
parameter location = "";
parameter mode = 0;
parameter path = 0;
parameter ring = 0;
wire clock = CK ^ dff_edge;
wire load = dff_load ? L : 1'b1;
wire async_reset = !dff_sync && dff_init && R;
wire sync_reset = dff_sync && dff_init && R;
reg O_reg;
always @(posedge clock, posedge async_reset)
if (async_reset) O_reg <= dff_type;
else if (sync_reset) O_reg <= dff_type;
else if (load) O_reg <= I;
assign O = data_inv ? O_reg : ~O_reg;
endmodule
(* abc9_box, lib_whitebox *) (* abc9_box, lib_whitebox *)
module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO); module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO);
parameter add_carry = 0; parameter add_carry = 0;