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Add `undef DSP48E1_INST

This commit is contained in:
Eddie Hung 2019-09-13 17:07:18 -07:00
parent 61877e1370
commit 681be20ca2
1 changed files with 5 additions and 4 deletions
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9
techlibs/xilinx/abc_map.v
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@ -207,7 +207,7 @@ module DSP48E1 (
parameter _TECHMAP_CELLTYPE_ = ""; parameter _TECHMAP_CELLTYPE_ = "";
localparam techmap_guard = (_TECHMAP_CELLTYPE_ != ""); localparam techmap_guard = (_TECHMAP_CELLTYPE_ != "");
`define DSP48E1_inst(__CELL__) """ `define DSP48E1_INST(__CELL__) """
__CELL__ #( __CELL__ #(
.ACASCREG(ACASCREG), .ACASCREG(ACASCREG),
.ADREG(ADREG), .ADREG(ADREG),
@ -336,7 +336,7 @@ __CELL__ #(
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
); );
`DSP48E1_inst(\$__ABC_DSP48E1_MULT ) `DSP48E1_INST(\$__ABC_DSP48E1_MULT )
end end
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") begin
wire [29:0] iA; wire [29:0] iA;
@ -381,7 +381,7 @@ __CELL__ #(
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
); );
`DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT ) `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT )
end end
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") begin
wire [29:0] iA; wire [29:0] iA;
@ -422,9 +422,10 @@ __CELL__ #(
.Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT) .Aq(pA), .Bq(pB), .Cq(pC), .Dq(pD), .ADq(pAD), .Mq(pM), .P(oPCOUT), .Pq(pP), .O(PCOUT)
); );
`DSP48E1_inst(\$__ABC_DSP48E1_MULTD_PORT ) `DSP48E1_INST(\$__ABC_DSP48E1_MULTD_PORT )
end end
else else
$error("Invalid DSP48E1 configuration"); $error("Invalid DSP48E1 configuration");
endgenerate endgenerate
`undef DSP48E1_INST
endmodule endmodule