mirror of https://github.com/YosysHQ/yosys.git
Revert formatting changes.
This commit is contained in:
Rasmus Munk Larsen
Lofty
parent
abd9c51963
commit
67f1700486
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@ -18,10 +18,10 @@
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*/
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#include "simplemap.h"
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#include "kernel/ff.h"
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#include "kernel/sigtools.h"
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#include <stdio.h>
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#include "kernel/ff.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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USING_YOSYS_NAMESPACE
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@ -64,16 +64,11 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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IdString gate_type;
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if (cell->type == ID($and))
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gate_type = ID($_AND_);
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if (cell->type == ID($or))
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gate_type = ID($_OR_);
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if (cell->type == ID($xor))
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gate_type = ID($_XOR_);
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if (cell->type == ID($xnor))
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gate_type = ID($_XNOR_);
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if (cell->type == ID($bweqx))
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gate_type = ID($_XNOR_);
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if (cell->type == ID($and)) gate_type = ID($_AND_);
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if (cell->type == ID($or)) gate_type = ID($_OR_);
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if (cell->type == ID($xor)) gate_type = ID($_XOR_);
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if (cell->type == ID($xnor)) gate_type = ID($_XNOR_);
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if (cell->type == ID($bweqx)) gate_type = ID($_XNOR_);
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log_assert(!gate_type.empty());
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for (int i = 0; i < GetSize(sig_y); i++) {
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@ -94,16 +89,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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return;
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if (sig_a.size() == 0) {
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if (cell->type == ID($reduce_and))
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module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == ID($reduce_or))
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module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == ID($reduce_xor))
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module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == ID($reduce_xnor))
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module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == ID($reduce_bool))
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module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == ID($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == ID($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == ID($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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return;
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}
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@ -113,24 +103,21 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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IdString gate_type;
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if (cell->type == ID($reduce_and))
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gate_type = ID($_AND_);
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if (cell->type == ID($reduce_or))
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gate_type = ID($_OR_);
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if (cell->type == ID($reduce_xor))
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gate_type = ID($_XOR_);
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if (cell->type == ID($reduce_xnor))
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gate_type = ID($_XOR_);
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if (cell->type == ID($reduce_bool))
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gate_type = ID($_OR_);
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if (cell->type == ID($reduce_and)) gate_type = ID($_AND_);
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if (cell->type == ID($reduce_or)) gate_type = ID($_OR_);
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if (cell->type == ID($reduce_xor)) gate_type = ID($_XOR_);
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if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_);
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if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_);
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log_assert(!gate_type.empty());
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RTLIL::Cell *last_output_cell = NULL;
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while (sig_a.size() > 1) {
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while (sig_a.size() > 1)
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
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for (int i = 0; i < sig_a.size(); i += 2) {
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for (int i = 0; i < sig_a.size(); i += 2)
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{
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if (i+1 == sig_a.size()) {
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sig_t.append(sig_a[i]);
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continue;
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@ -166,10 +153,12 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell *cell)
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{
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while (sig.size() > 1) {
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while (sig.size() > 1)
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
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for (int i = 0; i < sig.size(); i += 2) {
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for (int i = 0; i < sig.size(); i += 2)
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{
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if (i+1 == sig.size()) {
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sig_t.append(sig[i]);
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continue;
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@ -229,10 +218,8 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
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}
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IdString gate_type;
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if (cell->type == ID($logic_and))
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gate_type = ID($_AND_);
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if (cell->type == ID($logic_or))
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gate_type = ID($_OR_);
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if (cell->type == ID($logic_and)) gate_type = ID($_AND_);
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if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
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log_assert(!gate_type.empty());
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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@ -253,21 +240,18 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
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RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
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RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
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xor_cell->attributes[ID::src] = cell->attributes[ID::src];
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// xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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simplemap_bitop(module, xor_cell);
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module->remove(xor_cell);
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RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
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RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
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reduce_cell->attributes[ID::src] = cell->attributes[ID::src];
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// reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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simplemap_reduce(module, reduce_cell);
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module->remove(reduce_cell);
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if (!is_ne) {
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RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
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not_cell->attributes[ID::src] = cell->attributes[ID::src];
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// not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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simplemap_lognot(module, not_cell);
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module->remove(not_cell);
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}
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@ -17,14 +17,14 @@
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*
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*/
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#include "kernel/ffinit.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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#include "kernel/yosys.h"
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#include "kernel/utils.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "libs/sha1/sha1.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include "simplemap.h"
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@ -60,7 +60,8 @@ void apply_prefix(IdString prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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sig = chunks;
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}
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struct TechmapWorker {
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struct TechmapWorker
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{
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dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
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dict<std::pair<IdString, dict<IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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dict<RTLIL::Module*, bool> techmap_do_cache;
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@ -98,8 +99,8 @@ struct TechmapWorker {
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if (verbose)
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log(" Bit %d of port %s and bit %d of port %s are connected.\n", i, log_id(conn.first),
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connbits_map.at(bit).second, log_id(connbits_map.at(bit).first));
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constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i, log_id(connbits_map.at(bit).first),
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connbits_map.at(bit).second);
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constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
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log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
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} else {
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connbits_map.emplace(bit, std::make_pair(conn.first, i));
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constmap_info += stringf("|%s %d", log_id(conn.first), i);
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@ -155,7 +156,6 @@ struct TechmapWorker {
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}
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std::string orig_cell_name;
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orig_cell_name = cell->name.str();
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for (auto tpl_cell : tpl->cells())
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if (tpl_cell->name.ends_with("_TECHMAP_REPLACE_")) {
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@ -164,6 +164,7 @@ struct TechmapWorker {
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}
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dict<IdString, IdString> memory_renames;
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for (auto &it : tpl->memories) {
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IdString m_name = it.first;
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apply_prefix(cell->name, m_name);
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@ -178,14 +179,17 @@ struct TechmapWorker {
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dict<Wire*, IdString> temp_renamed_wires;
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pool<SigBit> autopurge_tpl_bits;
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for (auto tpl_w : tpl->wires()) {
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if (tpl_w->port_id > 0) {
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for (auto tpl_w : tpl->wires())
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{
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if (tpl_w->port_id > 0)
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{
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IdString posportname = stringf("$%d", tpl_w->port_id);
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positional_ports.emplace(posportname, tpl_w->name);
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if (tpl_w->get_bool_attribute(ID::techmap_autopurge) &&
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(!cell->hasPort(tpl_w->name) || !GetSize(cell->getPort(tpl_w->name))) &&
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(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname)))) {
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(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
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{
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if (sigmaps.count(tpl) == 0)
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sigmaps[tpl].set(tpl);
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@ -234,14 +238,14 @@ struct TechmapWorker {
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SigMap port_signal_map;
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for (auto &it : cell->connections()) {
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for (auto &it : cell->connections())
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{
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IdString portname = it.first;
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if (positional_ports.count(portname) > 0)
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portname = positional_ports.at(portname);
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if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {
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if (portname.begins_with("$"))
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(),
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tpl->name.c_str());
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
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continue;
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}
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@ -291,7 +295,8 @@ struct TechmapWorker {
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if (w->port_output && !w->port_input) {
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port_signal_map.add(c.second, c.first);
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} else if (!w->port_output && w->port_input) {
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} else
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if (!w->port_output && w->port_input) {
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port_signal_map.add(c.first, c.second);
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} else {
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module->connect(c);
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@ -312,7 +317,8 @@ struct TechmapWorker {
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}
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}
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for (auto tpl_cell : tpl->cells()) {
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for (auto tpl_cell : tpl->cells())
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{
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IdString c_name = tpl_cell->name;
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bool techmap_replace_cell = c_name.ends_with("_TECHMAP_REPLACE_");
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@ -331,7 +337,8 @@ struct TechmapWorker {
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vector<IdString> autopurge_ports;
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for (auto &conn : c->connections()) {
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for (auto &conn : c->connections())
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{
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bool autopurge = false;
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if (!autopurge_tpl_bits.empty()) {
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autopurge = GetSize(conn.second) != 0;
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@ -387,7 +394,8 @@ struct TechmapWorker {
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module->remove(cell);
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for (auto &it : temp_renamed_wires) {
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for (auto &it : temp_renamed_wires)
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{
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Wire *w = it.first;
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IdString name = it.second;
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IdString altname = module->uniquify(name);
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@ -416,7 +424,8 @@ struct TechmapWorker {
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dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_to_inbit;
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dict<RTLIL::SigBit, pool<RTLIL::Cell*>> outbit_to_cell;
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for (auto cell : module->selected_cells()) {
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for (auto cell : module->selected_cells())
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{
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if (handled_cells.count(cell) > 0)
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continue;
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@ -430,7 +439,8 @@ struct TechmapWorker {
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continue;
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}
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for (auto &conn : cell->connections()) {
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for (auto &conn : cell->connections())
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{
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RTLIL::SigSpec sig = sigmap(conn.second);
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sig.remove_const();
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@ -458,7 +468,8 @@ struct TechmapWorker {
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cells.sort();
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for (auto cell : cells.sorted) {
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for (auto cell : cells.sorted)
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{
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log_assert(handled_cells.count(cell) == 0);
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log_assert(cell == module->cell(cell->name));
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bool mapped_cell = false;
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@ -468,7 +479,8 @@ struct TechmapWorker {
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if (in_recursion && cell->type.begins_with("\\$"))
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cell_type = cell_type.substr(1);
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for (auto &tpl_name : celltypeMap.at(cell_type)) {
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for (auto &tpl_name : celltypeMap.at(cell_type))
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{
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IdString derived_name = tpl_name;
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RTLIL::Module *tpl = map->module(tpl_name);
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dict<IdString, RTLIL::Const> parameters(cell->parameters);
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@ -487,10 +499,12 @@ struct TechmapWorker {
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if (tpl->attributes.count(ID::techmap_wrap))
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extmapper_name = "wrap";
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if (!extmapper_name.empty()) {
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if (!extmapper_name.empty())
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{
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cell->type = cell_type;
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if ((extern_mode && !in_recursion) || extmapper_name == "wrap") {
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if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
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{
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std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
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for (auto &c : cell->parameters)
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@ -502,7 +516,8 @@ struct TechmapWorker {
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RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
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RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
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if (extmapper_module == nullptr) {
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if (extmapper_module == nullptr)
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{
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extmapper_module = extmapper_design->addModule(m_name);
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RTLIL::Cell *extmapper_cell = extmapper_module->addCell(cell->type, cell);
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@ -525,8 +540,7 @@ struct TechmapWorker {
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if (extmapper_name == "simplemap") {
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log("Creating %s with simplemap.\n", log_id(extmapper_module));
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if (simplemap_mappers.count(extmapper_cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n",
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log_id(extmapper_cell->type));
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log_error("No simplemap mapper for cell type %s found!\n", log_id(extmapper_cell->type));
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simplemap_mappers.at(extmapper_cell->type)(extmapper_module, extmapper_cell);
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extmapper_module->remove(extmapper_cell);
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}
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@ -534,8 +548,7 @@ struct TechmapWorker {
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if (extmapper_name == "maccmap") {
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log("Creating %s with maccmap.\n", log_id(extmapper_module));
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if (extmapper_cell->type != ID($macc))
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log_error("The maccmap mapper can only map $macc (not %s) cells!\n",
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log_id(extmapper_cell->type));
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log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(extmapper_cell->type));
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maccmap(extmapper_module, extmapper_cell);
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extmapper_module->remove(extmapper_cell);
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}
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@ -557,23 +570,21 @@ struct TechmapWorker {
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goto use_wrapper_tpl;
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}
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auto msg =
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stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
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auto msg = stringf("Using extmapper %s for cells of type %s.", log_id(extmapper_module), log_id(cell->type));
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if (!log_msg_cache.count(msg)) {
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log_msg_cache.insert(msg);
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log("%s\n", msg.c_str());
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}
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log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell),
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log_id(cell->type), log_id(extmapper_module));
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} else {
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auto msg =
|
||||
stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
|
||||
log_debug("%s %s.%s (%s) to %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(extmapper_module));
|
||||
}
|
||||
else
|
||||
{
|
||||
auto msg = stringf("Using extmapper %s for cells of type %s.", extmapper_name.c_str(), log_id(cell->type));
|
||||
if (!log_msg_cache.count(msg)) {
|
||||
log_msg_cache.insert(msg);
|
||||
log("%s\n", msg.c_str());
|
||||
}
|
||||
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell),
|
||||
log_id(cell->type), extmapper_name.c_str());
|
||||
log_debug("%s %s.%s (%s) with %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), extmapper_name.c_str());
|
||||
|
||||
if (extmapper_name == "simplemap") {
|
||||
if (simplemap_mappers.count(cell->type) == 0)
|
||||
|
|
@ -583,8 +594,7 @@ struct TechmapWorker {
|
|||
|
||||
if (extmapper_name == "maccmap") {
|
||||
if (cell->type != ID($macc))
|
||||
log_error("The maccmap mapper can only map $macc (not %s) cells!\n",
|
||||
log_id(cell->type));
|
||||
log_error("The maccmap mapper can only map $macc (not %s) cells!\n", log_id(cell->type));
|
||||
maccmap(module, cell);
|
||||
}
|
||||
|
||||
|
|
@ -602,8 +612,7 @@ struct TechmapWorker {
|
|||
continue;
|
||||
if (tpl->wire(conn.first) != nullptr && tpl->wire(conn.first)->port_id > 0)
|
||||
continue;
|
||||
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 ||
|
||||
tpl->avail_parameters.count(conn.first) == 0)
|
||||
if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
|
||||
goto next_tpl;
|
||||
parameters[conn.first] = conn.second.as_const();
|
||||
}
|
||||
|
|
@ -623,16 +632,14 @@ struct TechmapWorker {
|
|||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
bit = RTLIL::SigBit(bit.wire == nullptr ? RTLIL::State::S1 : RTLIL::State::S0);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)),
|
||||
RTLIL::SigSpec(v).as_const());
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTMSK_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first))) != 0) {
|
||||
std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
|
||||
for (auto &bit : v)
|
||||
if (bit.wire != nullptr)
|
||||
bit = RTLIL::SigBit(RTLIL::State::Sx);
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)),
|
||||
RTLIL::SigSpec(v).as_const());
|
||||
parameters.emplace(stringf("\\_TECHMAP_CONSTVAL_%s_", log_id(conn.first)), RTLIL::SigSpec(v).as_const());
|
||||
}
|
||||
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first))) != 0) {
|
||||
parameters.emplace(stringf("\\_TECHMAP_WIREINIT_%s_", log_id(conn.first)), initvals(conn.second));
|
||||
|
|
@ -701,13 +708,15 @@ struct TechmapWorker {
|
|||
if (constmapped_tpl != nullptr)
|
||||
tpl = constmapped_tpl;
|
||||
|
||||
if (techmap_do_cache.count(tpl) == 0) {
|
||||
if (techmap_do_cache.count(tpl) == 0)
|
||||
{
|
||||
bool keep_running = true;
|
||||
techmap_do_cache[tpl] = true;
|
||||
|
||||
pool<IdString> techmap_wire_names;
|
||||
|
||||
while (keep_running) {
|
||||
while (keep_running)
|
||||
{
|
||||
TechmapWires twd = techmap_find_special_wires(tpl);
|
||||
keep_running = false;
|
||||
|
||||
|
|
@ -720,8 +729,7 @@ struct TechmapWorker {
|
|||
for (const TechmapWireData &elem : it.second) {
|
||||
RTLIL::SigSpec value = elem.value;
|
||||
if (value.is_fully_const() && value.as_bool()) {
|
||||
log("Not using module `%s' from techmap as it contains a %s marker wire with "
|
||||
"non-zero value %s.\n",
|
||||
log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
|
||||
derived_name.c_str(), log_id(elem.wire->name), log_signal(value));
|
||||
techmap_do_cache[tpl] = false;
|
||||
}
|
||||
|
|
@ -731,15 +739,15 @@ struct TechmapWorker {
|
|||
if (!techmap_do_cache[tpl])
|
||||
break;
|
||||
|
||||
for (auto &it : twd) {
|
||||
for (auto &it : twd)
|
||||
{
|
||||
if (!it.first.contains("_TECHMAP_DO_") || it.second.empty())
|
||||
continue;
|
||||
|
||||
auto &data = it.second.front();
|
||||
|
||||
if (!data.value.is_fully_const())
|
||||
log_error("Techmap yielded config wire %s with non-const value %s.\n",
|
||||
log_id(data.wire->name), log_signal(data.value));
|
||||
log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(data.wire->name), log_signal(data.value));
|
||||
|
||||
techmap_wire_names.erase(it.first);
|
||||
|
||||
|
|
@ -750,7 +758,8 @@ struct TechmapWorker {
|
|||
std::string cmd_string = data.value.as_const().decode_string();
|
||||
|
||||
restart_eval_cmd_string:
|
||||
if (cmd_string.rfind("CONSTMAP; ", 0) == 0) {
|
||||
if (cmd_string.rfind("CONSTMAP; ", 0) == 0)
|
||||
{
|
||||
cmd_string = cmd_string.substr(strlen("CONSTMAP; "));
|
||||
|
||||
log("Analyzing pattern of constant bits for this cell:\n");
|
||||
|
|
@ -769,7 +778,8 @@ struct TechmapWorker {
|
|||
dict<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
|
||||
dict<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
|
||||
|
||||
for (auto wire : tpl->wires().to_vector()) {
|
||||
for (auto wire : tpl->wires().to_vector())
|
||||
{
|
||||
if (!wire->port_input || wire->port_output)
|
||||
continue;
|
||||
|
||||
|
|
@ -781,15 +791,14 @@ struct TechmapWorker {
|
|||
wire->port_id = 0;
|
||||
|
||||
for (int i = 0; i < wire->width; i++) {
|
||||
port_new2old_map.emplace(RTLIL::SigBit(new_wire, i),
|
||||
RTLIL::SigBit(wire, i));
|
||||
port_connmap.emplace(RTLIL::SigBit(wire, i),
|
||||
RTLIL::SigBit(new_wire, i));
|
||||
port_new2old_map.emplace(RTLIL::SigBit(new_wire, i), RTLIL::SigBit(wire, i));
|
||||
port_connmap.emplace(RTLIL::SigBit(wire, i), RTLIL::SigBit(new_wire, i));
|
||||
}
|
||||
}
|
||||
|
||||
// Handle outputs first, as these cannot be remapped.
|
||||
for (auto &conn : cell->connections()) {
|
||||
for (auto &conn : cell->connections())
|
||||
{
|
||||
Wire *twire = tpl->wire(conn.first);
|
||||
if (!twire->port_output)
|
||||
continue;
|
||||
|
|
@ -802,22 +811,28 @@ struct TechmapWorker {
|
|||
}
|
||||
|
||||
// Now handle inputs, remapping as necessary.
|
||||
for (auto &conn : cell->connections()) {
|
||||
for (auto &conn : cell->connections())
|
||||
{
|
||||
Wire *twire = tpl->wire(conn.first);
|
||||
if (twire->port_output)
|
||||
continue;
|
||||
|
||||
for (int i = 0; i < GetSize(conn.second); i++) {
|
||||
for (int i = 0; i < GetSize(conn.second); i++)
|
||||
{
|
||||
RTLIL::SigBit bit = sigmap(conn.second[i]);
|
||||
RTLIL::SigBit tplbit(twire, i);
|
||||
|
||||
if (bit.wire == nullptr) {
|
||||
if (bit.wire == nullptr)
|
||||
{
|
||||
RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
|
||||
port_connmap.at(oldbit) = bit;
|
||||
} else if (cellbits_to_tplbits.count(bit)) {
|
||||
}
|
||||
else if (cellbits_to_tplbits.count(bit))
|
||||
{
|
||||
RTLIL::SigBit oldbit = port_new2old_map.at(tplbit);
|
||||
port_connmap.at(oldbit) = cellbits_to_tplbits[bit];
|
||||
} else
|
||||
}
|
||||
else
|
||||
cellbits_to_tplbits[bit] = tplbit;
|
||||
}
|
||||
}
|
||||
|
|
@ -833,18 +848,17 @@ struct TechmapWorker {
|
|||
goto restart_eval_cmd_string;
|
||||
}
|
||||
|
||||
if (cmd_string.rfind("RECURSION; ", 0) == 0) {
|
||||
if (cmd_string.rfind("RECURSION; ", 0) == 0)
|
||||
{
|
||||
cmd_string = cmd_string.substr(strlen("RECURSION; "));
|
||||
while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) {
|
||||
}
|
||||
while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
|
||||
goto restart_eval_cmd_string;
|
||||
}
|
||||
|
||||
Pass::call_on_module(map, tpl, cmd_string);
|
||||
|
||||
log_assert(!strncmp(q, "_TECHMAP_DO_", 12));
|
||||
std::string new_name =
|
||||
data.wire->name.substr(0, q - p) + "_TECHMAP_DONE_" + data.wire->name.substr(q - p + 12);
|
||||
std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
|
||||
while (tpl->wire(new_name) != nullptr)
|
||||
new_name += "_";
|
||||
tpl->rename(data.wire->name, new_name);
|
||||
|
|
@ -856,15 +870,12 @@ struct TechmapWorker {
|
|||
|
||||
TechmapWires twd = techmap_find_special_wires(tpl);
|
||||
for (auto &it : twd) {
|
||||
if (!it.first.ends_with("_TECHMAP_FAIL_") &&
|
||||
(!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) &&
|
||||
!it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_"))
|
||||
if (!it.first.ends_with("_TECHMAP_FAIL_") && (!it.first.begins_with("\\_TECHMAP_REMOVEINIT_") || !it.first.ends_with("_")) && !it.first.contains("_TECHMAP_DO_") && !it.first.contains("_TECHMAP_DONE_"))
|
||||
log_error("Techmap yielded unknown config wire %s.\n", log_id(it.first));
|
||||
if (techmap_do_cache[tpl])
|
||||
for (auto &it2 : it.second)
|
||||
if (!it2.value.is_fully_const())
|
||||
log_error("Techmap yielded config wire %s with non-const value %s.\n",
|
||||
log_id(it2.wire->name), log_signal(it2.value));
|
||||
log_error("Techmap yielded config wire %s with non-const value %s.\n", log_id(it2.wire->name), log_signal(it2.value));
|
||||
techmap_wire_names.erase(it.first);
|
||||
}
|
||||
|
||||
|
|
@ -877,8 +888,7 @@ struct TechmapWorker {
|
|||
log_continue = false;
|
||||
mkdebug.off();
|
||||
}
|
||||
while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) {
|
||||
}
|
||||
while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -908,10 +918,12 @@ struct TechmapWorker {
|
|||
}
|
||||
}
|
||||
|
||||
if (extern_mode && !in_recursion) {
|
||||
if (extern_mode && !in_recursion)
|
||||
{
|
||||
std::string m_name = stringf("$extern:%s", log_id(tpl));
|
||||
|
||||
if (!design->module(m_name)) {
|
||||
if (!design->module(m_name))
|
||||
{
|
||||
RTLIL::Module *m = design->addModule(m_name);
|
||||
tpl->cloneInto(m);
|
||||
|
||||
|
|
@ -926,14 +938,15 @@ struct TechmapWorker {
|
|||
log_debug("%s %s.%s to imported %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(m_name));
|
||||
cell->type = m_name;
|
||||
cell->parameters.clear();
|
||||
} else {
|
||||
}
|
||||
else
|
||||
{
|
||||
auto msg = stringf("Using template %s for cells of type %s.", log_id(tpl), log_id(cell->type));
|
||||
if (!log_msg_cache.count(msg)) {
|
||||
log_msg_cache.insert(msg);
|
||||
log("%s\n", msg.c_str());
|
||||
}
|
||||
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell),
|
||||
log_id(cell->type), log_id(tpl));
|
||||
log_debug("%s %s.%s (%s) using %s.\n", mapmsg_prefix.c_str(), log_id(module), log_id(cell), log_id(cell->type), log_id(tpl));
|
||||
techmap_module_worker(design, module, cell, tpl);
|
||||
cell = nullptr;
|
||||
}
|
||||
|
|
@ -1194,9 +1207,7 @@ struct TechmapPass : public Pass {
|
|||
if (!map->module(mod->name))
|
||||
map->add(mod->clone());
|
||||
} else {
|
||||
Frontend::frontend_call(
|
||||
map, nullptr, fn,
|
||||
(fn.size() > 3 && fn.compare(fn.size() - 3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));
|
||||
Frontend::frontend_call(map, nullptr, fn, (fn.size() > 3 && fn.compare(fn.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : verilog_frontend));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1222,15 +1233,15 @@ struct TechmapPass : public Pass {
|
|||
if (epos == std::string::npos)
|
||||
log_error("Malformed techmap_celltype pattern %s\n", q);
|
||||
for (size_t i = pos + 1; i < epos; i++) {
|
||||
queue.push_back(name.substr(0, pos) + name[i] +
|
||||
name.substr(epos + 1, std::string::npos));
|
||||
queue.push_back(name.substr(0, pos) + name[i] + name.substr(epos + 1, std::string::npos));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
free(p);
|
||||
} else {
|
||||
IdString module_name = module->name.begins_with("\\$") ? module->name.substr(1) : module->name.str();
|
||||
IdString module_name = module->name.begins_with("\\$") ?
|
||||
module->name.substr(1) : module->name.str();
|
||||
celltypeMap[module_name].insert(module->name);
|
||||
}
|
||||
}
|
||||
|
|
@ -1247,7 +1258,8 @@ struct TechmapPass : public Pass {
|
|||
for (auto module : design->modules())
|
||||
worker.module_queue.insert(module);
|
||||
|
||||
while (!worker.module_queue.empty()) {
|
||||
while (!worker.module_queue.empty())
|
||||
{
|
||||
RTLIL::Module *module = *worker.module_queue.begin();
|
||||
worker.module_queue.erase(module);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue