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Only generate write-enable $and if WE is not constant 1 in memory_map

This commit is contained in:
Clifford Wolf 2014-02-02 21:27:26 +01:00
parent 83fa652820
commit 67b0ce2578
1 changed files with 18 additions and 15 deletions
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33
passes/memory/memory_map.cc
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@ -273,22 +273,25 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
module->wires[w->name] = w; module->wires[w->name] = w;
c->connections["\\Y"] = RTLIL::SigSpec(w); c->connections["\\Y"] = RTLIL::SigSpec(w);
c = new RTLIL::Cell; if (wr_en != RTLIL::SigSpec(1, 1))
c->name = genid(cell->name, "$wren", i, "", j); {
c->type = "$and"; c = new RTLIL::Cell;
c->parameters["\\A_SIGNED"] = RTLIL::Const(0); c->name = genid(cell->name, "$wren", i, "", j);
c->parameters["\\B_SIGNED"] = RTLIL::Const(0); c->type = "$and";
c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
c->connections["\\A"] = RTLIL::SigSpec(w); c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
c->connections["\\B"] = wr_en; c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->cells[c->name] = c; c->connections["\\A"] = RTLIL::SigSpec(w);
c->connections["\\B"] = wr_en;
module->cells[c->name] = c;
w = new RTLIL::Wire; w = new RTLIL::Wire;
w->name = genid(cell->name, "$wren", i, "", j, "$y"); w->name = genid(cell->name, "$wren", i, "", j, "$y");
module->wires[w->name] = w; module->wires[w->name] = w;
c->connections["\\Y"] = RTLIL::SigSpec(w); c->connections["\\Y"] = RTLIL::SigSpec(w);
}
c = new RTLIL::Cell; c = new RTLIL::Cell;
c->name = genid(cell->name, "$wrmux", i, "", j); c->name = genid(cell->name, "$wrmux", i, "", j);