mirror of https://github.com/YosysHQ/yosys.git
passes/hierarchy: delete some dead code
Signed-off-by: Austin Seipp <aseipp@pobox.com>
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parent
78f65f89ff
commit
6781543244
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@ -175,16 +175,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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{
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{
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filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v";
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filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v";
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if (check_file_exists(filename)) {
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if (check_file_exists(filename)) {
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std::vector<std::string> args;
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args.push_back(filename);
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Frontend::frontend_call(design, NULL, filename, "verilog");
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Frontend::frontend_call(design, NULL, filename, "verilog");
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goto loaded_module;
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goto loaded_module;
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}
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}
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filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il";
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filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il";
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if (check_file_exists(filename)) {
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if (check_file_exists(filename)) {
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std::vector<std::string> args;
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args.push_back(filename);
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Frontend::frontend_call(design, NULL, filename, "ilang");
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Frontend::frontend_call(design, NULL, filename, "ilang");
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goto loaded_module;
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goto loaded_module;
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}
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}
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