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Merge pull request #2835 from YosysHQ/verific_command 

Support command files in Verific
This commit is contained in:
Claire Xen 2021-07-05 16:59:37 +02:00 committed by GitHub
parent 75e5500d4d 0dbb05a75e
commit 676c544abe
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 61 additions and 0 deletions
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61
frontends/verific/verific.cc
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@ -2084,6 +2084,32 @@ struct VerificPass : public Pass {
log("Load the specified VHDL files into Verific.\n");
log("\n");
log("\n");
log(" verific {-f|-F} <command-file>\n");
log("\n");
log("Load and execute the specified command file.\n");
log("\n");
log("Command file parser supports following commands:\n");
log(" +define - defines macro\n");
log(" -u - upper case all identifier (makes Verilog parser case insensitive)\n");
log(" -v - register library name (file)\n");
log(" -y - register library name (directory)\n");
log(" +incdir - specify include dir\n");
log(" +libext - specify library extension\n");
log(" +liborder - add library in ordered list\n");
log(" +librescan - unresolved modules will be always searched starting with the first\n");
log(" library specified by -y/-v options.\n");
log(" -f/-file - nested -f option\n");
log(" -F - nested -F option\n");
log("\n");
log(" parse mode:\n");
log(" -ams\n");
log(" +systemverilogext\n");
log(" +v2k\n");
log(" +verilog1995ext\n");
log(" +verilog2001ext\n");
log(" -sverilog\n");
log("\n");
log("\n");
log(" verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
log("\n");
log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
@ -2407,6 +2433,25 @@ struct VerificPass : public Pass {
break;
}
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{
unsigned verilog_mode = veri_file::VERILOG_95; // default recommended by Verific
Verific::veri_file::f_file_flags flags = (args[argidx] == "-f") ? veri_file::F_FILE_NONE : veri_file::F_FILE_CAPITAL;
Array *file_names = veri_file::ProcessFFile(args[++argidx].c_str(), flags, verilog_mode);
veri_file::DefineMacro("VERIFIC");
if (!veri_file::AnalyzeMultipleFiles(file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
verific_error_msg.clear();
log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
}
delete file_names;
verific_import_pending = true;
goto check_error;
}
if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
{
@ -2963,6 +3008,12 @@ struct ReadPass : public Pass {
log("Load the specified VHDL files. (Requires Verific.)\n");
log("\n");
log("\n");
log(" read {-f|-F} <command-file>\n");
log("\n");
log("Load and execute the specified command file. (Requires Verific.)\n");
log("Check verific command for more information about supported commands in file.\n");
log("\n");
log("\n");
log(" read -define <macro>[=<value>]..\n");
log("\n");
log("Set global Verilog/SystemVerilog defines.\n");
@ -3049,6 +3100,16 @@ struct ReadPass : public Pass {
return;
}
if (args[1] == "-f" || args[1] == "-F") {
if (use_verific) {
args[0] = "verific";
Pass::call(design, args);
} else {
cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
}
return;
}
if (args[1] == "-define") {
if (use_verific) {
args[0] = "verific";