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Added RTLIL::Module::wire(id) and cell(id) lookup functions

This commit is contained in:
Clifford Wolf 2014-07-27 11:03:56 +02:00
parent 0bd8fafbd2
commit 675cb93da9
2 changed files with 20 additions and 2 deletions
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12
kernel/rtlil.cc
View File

@ -274,6 +274,16 @@ bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString me
return selection_stack.back().selected_member(mod_name, memb_name); return selection_stack.back().selected_member(mod_name, memb_name);
} }
bool RTLIL::Design::selected_module(RTLIL::Module *mod) const
{
return selected_module(mod->name);
}
bool RTLIL::Design::selected_whole_module(RTLIL::Module *mod) const
{
return selected_whole_module(mod->name);
}
RTLIL::Module::Module() RTLIL::Module::Module()
{ {
refcount_wires_ = 0; refcount_wires_ = 0;
@ -1502,6 +1512,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire) RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
{ {
log_assert(wire != nullptr);
this->wire = wire; this->wire = wire;
this->width = wire->width; this->width = wire->width;
this->offset = 0; this->offset = 0;
@ -1509,6 +1520,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire)
RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width) RTLIL::SigChunk::SigChunk(RTLIL::Wire *wire, int offset, int width)
{ {
log_assert(wire != nullptr);
this->wire = wire; this->wire = wire;
this->width = width; this->width = width;
this->offset = offset; this->offset = offset;

10
kernel/rtlil.h
View File

@ -358,6 +358,9 @@ struct RTLIL::Design
bool selected_whole_module(RTLIL::IdString mod_name) const; bool selected_whole_module(RTLIL::IdString mod_name) const;
bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const; bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
bool selected_module(RTLIL::Module *mod) const;
bool selected_whole_module(RTLIL::Module *mod) const;
bool full_selection() const { bool full_selection() const {
return selection_stack.back().full_selection; return selection_stack.back().full_selection;
} }
@ -425,6 +428,9 @@ public:
void cloneInto(RTLIL::Module *new_mod) const; void cloneInto(RTLIL::Module *new_mod) const;
virtual RTLIL::Module *clone() const; virtual RTLIL::Module *clone() const;
RTLIL::Wire* wire(RTLIL::IdString id) { return wires_.count(id) ? wires_.at(id) : nullptr; }
RTLIL::Cell* cell(RTLIL::IdString id) { return cells_.count(id) ? cells_.at(id) : nullptr; }
RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); } RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); } RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
@ -663,8 +669,8 @@ struct RTLIL::SigBit
SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { } SigBit() : wire(NULL), data(RTLIL::State::S0), offset(0) { }
SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit), offset(0) { }
SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(!wire || wire->width == 1); } SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0), offset(0) { assert(wire && wire->width == 1); }
SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), data(RTLIL::State::S0), offset(offset) { assert(wire); }
SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { assert(chunk.width == 1); } SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[0]), offset(chunk.offset) { assert(chunk.width == 1); }
SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire), data(chunk.wire ? RTLIL::State::S0 : chunk.data.bits[index]), offset(chunk.wire ? chunk.offset + index : 0) { }
SigBit(const RTLIL::SigSpec &sig); SigBit(const RTLIL::SigSpec &sig);