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Add specify support to README 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2019-04-23 23:01:38 +02:00
parent 64925b4e8f
commit 67005633e2
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@ -424,6 +424,11 @@ Verilog Attributes and non-standard features
in an unconditional context (only if/case statements on parameters in an unconditional context (only if/case statements on parameters
and constant values). The intended use for this is synthesis-time DRC. and constant values). The intended use for this is synthesis-time DRC.
- There is limited support for converting specify .. endspecify statements to
special ``$specify2``, ``$specify3``, and ``$specrule`` cells, for use in
blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable this
functionality. (By default specify .. endspecify blocks are ignored.)
Non-standard or SystemVerilog features for formal verification Non-standard or SystemVerilog features for formal verification
============================================================== ==============================================================