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Some cleanups in opt_clean

This commit is contained in:
Clifford Wolf 2014-10-16 11:46:57 +02:00
parent 3838856a9e
commit 66eb254fc2
1 changed files with 9 additions and 16 deletions
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25
passes/opt/opt_clean.cc
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@ -35,18 +35,15 @@ int count_rm_cells, count_rm_wires;
void rmunused_module_cells(RTLIL::Module *module, bool verbose) void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{ {
SigMap assign_map(module); SigMap sigmap(module);
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused; std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver; SigSet<RTLIL::Cell*> wire2driver;
for (auto &it : module->cells_) { for (auto &it : module->cells_) {
RTLIL::Cell *cell = it.second; RTLIL::Cell *cell = it.second;
for (auto &it2 : cell->connections()) { for (auto &it2 : cell->connections()) {
if (!ct.cell_input(cell->type, it2.first)) { if (!ct.cell_input(cell->type, it2.first))
RTLIL::SigSpec sig = it2.second; wire2driver.insert(sigmap(it2.second), cell);
assign_map.apply(sig);
wire2driver.insert(sig, cell);
}
} }
if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr()) if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr())
queue.insert(cell); queue.insert(cell);
@ -57,15 +54,13 @@ void rmunused_module_cells(RTLIL::Module *module, bool verbose)
RTLIL::Wire *wire = it.second; RTLIL::Wire *wire = it.second;
if (wire->port_output || wire->get_bool_attribute("\\keep")) { if (wire->port_output || wire->get_bool_attribute("\\keep")) {
std::set<RTLIL::Cell*> cell_list; std::set<RTLIL::Cell*> cell_list;
RTLIL::SigSpec sig = RTLIL::SigSpec(wire); wire2driver.find(sigmap(wire), cell_list);
assign_map.apply(sig);
wire2driver.find(sig, cell_list);
for (auto cell : cell_list) for (auto cell : cell_list)
queue.insert(cell); queue.insert(cell);
} }
} }
while (queue.size() > 0) while (!queue.empty())
{ {
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue; std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> new_queue;
for (auto cell : queue) for (auto cell : queue)
@ -74,12 +69,10 @@ void rmunused_module_cells(RTLIL::Module *module, bool verbose)
for (auto &it : cell->connections()) { for (auto &it : cell->connections()) {
if (!ct.cell_output(cell->type, it.first)) { if (!ct.cell_output(cell->type, it.first)) {
std::set<RTLIL::Cell*> cell_list; std::set<RTLIL::Cell*> cell_list;
RTLIL::SigSpec sig = it.second; wire2driver.find(sigmap(it.second), cell_list);
assign_map.apply(sig); for (auto c : cell_list) {
wire2driver.find(sig, cell_list); if (unused.count(c))
for (auto cell : cell_list) { new_queue.insert(c);
if (unused.count(cell) > 0)
new_queue.insert(cell);
} }
} }
} }