mirror of https://github.com/YosysHQ/yosys.git
quicklogic: ql_dsp_simd remove unused MODE_BITS packing
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7514c4738a
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@ -61,9 +61,6 @@ struct QlDspSimdPass : public Pass {
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// ..........................................
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const int m_Dspv1ModeBitsSize = 80;
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const int m_Dspv2ModeBitsSize = 68;
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/// Temporary SigBit to SigBit helper map.
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SigMap sigmap;
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@ -110,12 +107,13 @@ struct QlDspSimdPass : public Pass {
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ID(shift_right_i),
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ID(subtract_i),
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ID(register_inputs_i),
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ID(coeff_0_i),
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ID(coeff_1_i),
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ID(coeff_2_i),
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ID(coeff_3_i),
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};
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static const std::vector<IdString> m_Dspv1CfgParams = {};
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static const std::vector<IdString> m_Dspv1CfgParams = {
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ID(COEFF_0),
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ID(COEFF_1),
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ID(COEFF_2),
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ID(COEFF_3),
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};
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static const std::vector<IdString> m_Dspv2CfgPorts = {
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ID(clock_i),
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ID(reset_i),
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@ -159,15 +157,6 @@ struct QlDspSimdPass : public Pass {
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ID(z_o),
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};
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// Params to serialize into MODE_BITS param
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static const std::vector<IdString> m_Dspv1ModeBitParams = {
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ID(COEFF_3),
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ID(COEFF_2),
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ID(COEFF_1),
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ID(COEFF_0),
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};
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static const std::vector<IdString> m_Dspv2ModeBitParams = {};
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// Source DSP cell type (half-block)
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static const IdString m_Dspv1SisdType = ID(dsp_t1_10x9x32_cfg_ports);
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static const IdString m_Dspv2SisdType = ID(dspv2_16x9x32_cfg_ports);
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@ -195,8 +184,6 @@ struct QlDspSimdPass : public Pass {
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const auto& data_ports = (dsp_version == 1) ? m_Dspv1DataPorts : m_Dspv2DataPorts;
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auto half_dsp = (dsp_version == 1) ? m_Dspv1SisdType : m_Dspv2SisdType;
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auto full_dsp = (dsp_version == 1) ? m_Dspv1SimdType : m_Dspv2SimdType;
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auto mode_bit_params = (dsp_version == 1) ? m_Dspv1ModeBitParams : m_Dspv2ModeBitParams;
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auto mode_bits_size = (dsp_version == 1) ? m_Dspv1ModeBitsSize : m_Dspv2ModeBitsSize;
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int cellsMerged = 0;
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// Process modules
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@ -300,27 +287,9 @@ struct QlDspSimdPass : public Pass {
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simd->setPort(port, sigspec);
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}
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if (mode_bit_params.size()) {
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// Concatenate FIR coefficient parameters into the single
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// MODE_BITS parameter
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Const mode_bits;
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for (const auto &it : mode_bit_params) {
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auto val_a = dsp_a->getParam(it);
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auto val_b = dsp_b->getParam(it);
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mode_bits.bits().insert(mode_bits.bits().end(),
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val_a.begin(), val_a.end());
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mode_bits.bits().insert(mode_bits.bits().end(),
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val_b.begin(), val_b.end());
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}
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simd->setParam(ID(MODE_BITS), mode_bits);
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log_assert(mode_bits.size() == mode_bits_size);
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}
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// Enable the fractured mode
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if (dsp_version == 1)
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simd->setPort(ID(f_mode), State::S1);
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simd->setPort(ID(f_mode_i), State::S1);
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else
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simd->setParam(ID(FRAC_MODE), State::S1);
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