From 6682693888148594c21bba3a75e1fe0ab6aef950 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 14 Aug 2023 16:20:36 +0200 Subject: [PATCH] change ql-bram-types pass to use mode parameter; clean up primitive libraries --- techlibs/quicklogic/Makefile.inc | 2 +- techlibs/quicklogic/ql-bram-merge.cc | 306 +- techlibs/quicklogic/ql-bram-types.cc | 165 + techlibs/quicklogic/qlf_k6n10f/arith_map.v | 46 +- .../quicklogic/qlf_k6n10f/bram_types_sim.v | 130881 ++++++++------- .../quicklogic/qlf_k6n10f/brams_final_map.v | 1144 +- techlibs/quicklogic/qlf_k6n10f/brams_map.v | 2406 +- techlibs/quicklogic/qlf_k6n10f/brams_sim.v | 12722 +- techlibs/quicklogic/qlf_k6n10f/cells_sim.v | 520 +- techlibs/quicklogic/qlf_k6n10f/ffs_map.v | 146 +- .../qlf_k6n10f/generate_bram_types_sim.py | 246 + techlibs/quicklogic/quicklogic_eqn.cc | 100 - techlibs/quicklogic/synth_quicklogic.cc | 74 +- 13 files changed, 74503 insertions(+), 74255 deletions(-) create mode 100644 techlibs/quicklogic/ql-bram-types.cc create mode 100644 techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py delete mode 100644 techlibs/quicklogic/quicklogic_eqn.cc diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index fcc49cd77..df69a3fc3 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,6 +1,6 @@ OBJS += techlibs/quicklogic/synth_quicklogic.o OBJS += techlibs/quicklogic/ql-bram-merge.o -OBJS += techlibs/quicklogic/quicklogic_eqn.o +OBJS += techlibs/quicklogic/ql-bram-types.o $(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) diff --git a/techlibs/quicklogic/ql-bram-merge.cc b/techlibs/quicklogic/ql-bram-merge.cc index d64bd64cf..1098bc8f6 100644 --- a/techlibs/quicklogic/ql-bram-merge.cc +++ b/techlibs/quicklogic/ql-bram-merge.cc @@ -31,184 +31,184 @@ PRIVATE_NAMESPACE_BEGIN struct QlBramMergeWorker { - const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); - const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); + const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); + const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); - // can be used to record parameter values that have to match on both sides - typedef dict MergeableGroupKeyType; + // can be used to record parameter values that have to match on both sides + typedef dict MergeableGroupKeyType; - RTLIL::Module *module; - dict> mergeable_groups; + RTLIL::Module *module; + dict> mergeable_groups; - QlBramMergeWorker(RTLIL::Module* module) : module(module) - { - for (RTLIL::Cell* cell : module->selected_cells()) - { - if(cell->type != split_cell_type) continue; - if(!cell->hasParam(ID(OPTION_SPLIT))) continue; - if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; - mergeable_groups[get_key(cell)].insert(cell); - } - } + QlBramMergeWorker(RTLIL::Module* module) : module(module) + { + for (RTLIL::Cell* cell : module->selected_cells()) + { + if(cell->type != split_cell_type) continue; + if(!cell->hasParam(ID(OPTION_SPLIT))) continue; + if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; + mergeable_groups[get_key(cell)].insert(cell); + } + } - static MergeableGroupKeyType get_key(RTLIL::Cell* cell) - { - MergeableGroupKeyType key; - // For now, there are no restrictions on which cells can be merged - (void) cell; - return key; - } + static MergeableGroupKeyType get_key(RTLIL::Cell* cell) + { + MergeableGroupKeyType key; + // For now, there are no restrictions on which cells can be merged + (void) cell; + return key; + } - const dict& param_map(bool second) - { - static const dict bram1_map = { - { ID(INIT), ID(INIT1) }, - { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, - { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, - { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, - { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } - }; - static const dict bram2_map = { - { ID(INIT), ID(INIT2) }, - { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, - { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, - { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, - { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } - }; + const dict& param_map(bool second) + { + static const dict bram1_map = { + { ID(INIT), ID(INIT1) }, + { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } + }; + static const dict bram2_map = { + { ID(INIT), ID(INIT2) }, + { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } + }; - if(second) - return bram2_map; - else - return bram1_map; - } + if(second) + return bram2_map; + else + return bram1_map; + } - const dict& port_map(bool second) - { - static const dict bram1_map = { - { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, - { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, - { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, - { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, - { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, - { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, - { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, - { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, - { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, - { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, - { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, - { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, - { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, - { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } - }; - static const dict bram2_map = { - { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, - { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, - { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, - { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, - { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, - { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, - { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, - { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, - { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, - { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, - { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, - { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, - { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, - { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } - }; + const dict& port_map(bool second) + { + static const dict bram1_map = { + { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } + }; + static const dict bram2_map = { + { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } + }; - if(second) - return bram2_map; - else - return bram1_map; - } + if(second) + return bram2_map; + else + return bram1_map; + } - void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) - { + void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) + { - // Create the new cell - RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); - log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); + // Create the new cell + RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); + log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); - for (auto &it : param_map(false)) - { - if(bram1->hasParam(it.first)) - merged->setParam(it.second, bram1->getParam(it.first)); - } - for (auto &it : param_map(true)) - { - if(bram2->hasParam(it.first)) - merged->setParam(it.second, bram2->getParam(it.first)); - } + for (auto &it : param_map(false)) + { + if(bram1->hasParam(it.first)) + merged->setParam(it.second, bram1->getParam(it.first)); + } + for (auto &it : param_map(true)) + { + if(bram2->hasParam(it.first)) + merged->setParam(it.second, bram2->getParam(it.first)); + } - for (auto &it : port_map(false)) - { - if (bram1->hasPort(it.first)) - merged->setPort(it.second, bram1->getPort(it.first)); - else - log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); - } - for (auto &it : port_map(true)) - { - if (bram2->hasPort(it.first)) - merged->setPort(it.second, bram2->getPort(it.first)); - else - log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); - } - merged->attributes = bram1->attributes; - for (auto attr: bram2->attributes) - if (!merged->has_attribute(attr.first)) - merged->attributes.insert(attr); + for (auto &it : port_map(false)) + { + if (bram1->hasPort(it.first)) + merged->setPort(it.second, bram1->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); + } + for (auto &it : port_map(true)) + { + if (bram2->hasPort(it.first)) + merged->setPort(it.second, bram2->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); + } + merged->attributes = bram1->attributes; + for (auto attr: bram2->attributes) + if (!merged->has_attribute(attr.first)) + merged->attributes.insert(attr); - // Remove the old cells - module->remove(bram1); - module->remove(bram2); + // Remove the old cells + module->remove(bram1); + module->remove(bram2); - } + } - void merge_bram_groups() - { - for (auto &it : mergeable_groups) - { - while (it.second.size() > 1) - { - merge_brams(it.second.pop(), it.second.pop()); - } - } - } + void merge_bram_groups() + { + for (auto &it : mergeable_groups) + { + while (it.second.size() > 1) + { + merge_brams(it.second.pop(), it.second.pop()); + } + } + } }; struct QlBramMergePass : public Pass { - - QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} + + QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" ql_bram_merge [selection]\n"); - log("\n"); - log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); - log(" into a TDP36K cell operating in split mode\n"); - log("\n"); - } + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_merge [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); + log(" into a TDP36K cell operating in split mode\n"); + log("\n"); + } - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing QL_BRAM_MERGE pass.\n"); + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_MERGE pass.\n"); - size_t argidx = 1; - extra_args(args, argidx, design); + size_t argidx = 1; + extra_args(args, argidx, design); - for (RTLIL::Module* module : design->selected_modules()) - { - QlBramMergeWorker worker(module); - worker.merge_bram_groups(); - } - } + for (RTLIL::Module* module : design->selected_modules()) + { + QlBramMergeWorker worker(module); + worker.merge_bram_groups(); + } + } } QlBramMergePass; diff --git a/techlibs/quicklogic/ql-bram-types.cc b/techlibs/quicklogic/ql-bram-types.cc new file mode 100644 index 000000000..cf42703aa --- /dev/null +++ b/techlibs/quicklogic/ql-bram-types.cc @@ -0,0 +1,165 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 N. Engelhardt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// ============================================================================ + + +struct QlBramTypesPass : public Pass { + + QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_types [selection]\n"); + log("\n"); + log(" This pass changes the type of TDP36K cells to different types based on the\n"); + log(" configuration of the cell.\n"); + log("\n"); + } + + int width_for_mode(int mode){ + // 1: mode = 3'b101; + // 2: mode = 3'b110; + // 4: mode = 3'b100; + // 8,9: mode = 3'b001; + // 16, 18: mode = 3'b010; + // 32, 36: mode = 3'b011; + switch (mode) + { + case 1: + return 9; + case 2: + return 18; + case 3: + return 36; + case 4: + return 4; + case 5: + return 1; + case 6: + return 2; + default: + log_error("Invalid mode: %x", mode); + } + } + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_TYPES pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + for (RTLIL::Cell* cell: module->selected_cells()) + { + if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS))) + continue; + + RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS)); + + bool split = mode_bits.extract(80).as_bool(); + + bool FMODE1_i = mode_bits.extract(13).as_bool(); + bool FMODE2_i = mode_bits.extract(54).as_bool(); + if (FMODE1_i != FMODE2_i) { + log_debug("Can't change type of mixed use TDP36K block: FMODE1_i = %s, FMODE2_i = %s\n", FMODE1_i ? "true" : "false", FMODE2_i ? "true" : "false"); + continue; + } + bool is_fifo = FMODE1_i; + + bool SYNC_FIFO1_i = mode_bits.extract(0).as_bool(); + bool SYNC_FIFO2_i = mode_bits.extract(41).as_bool(); + if (SYNC_FIFO1_i != SYNC_FIFO2_i) { + log_debug("Can't change type of mixed use TDP36K block: SYNC_FIFO1_i = %s, SYNC_FIFO2_i = %s\n", SYNC_FIFO1_i ? "true" : "false", SYNC_FIFO2_i ? "true" : "false"); + continue; + } + bool sync_fifo = SYNC_FIFO1_i; + + int RMODE_A1_i = mode_bits.extract(1, 3).as_int(); + int RMODE_B1_i = mode_bits.extract(4, 3).as_int(); + int WMODE_A1_i = mode_bits.extract(7, 3).as_int(); + int WMODE_B1_i = mode_bits.extract(10, 3).as_int(); + + int RMODE_A2_i = mode_bits.extract(42, 3).as_int(); + int RMODE_B2_i = mode_bits.extract(45, 3).as_int(); + int WMODE_A2_i = mode_bits.extract(48, 3).as_int(); + int WMODE_B2_i = mode_bits.extract(51, 3).as_int(); + + // TODO: should these be a warning or an error? + if (RMODE_A1_i != WMODE_A1_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port A1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A1_i), width_for_mode(WMODE_A1_i)); + continue; + } + if (RMODE_B1_i != WMODE_B1_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port B1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B1_i), width_for_mode(WMODE_B1_i)); + continue; + } + if (RMODE_A2_i != WMODE_A2_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port A2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A2_i), width_for_mode(WMODE_A2_i)); + continue; + } + if (RMODE_B2_i != WMODE_B2_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port B2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B2_i), width_for_mode(WMODE_B2_i)); + continue; + } + + // TODO: For nonsplit blocks, should RMODE_A1_i == RMODE_A2_i etc be checked/enforced? + + std::string type = "TDP36K"; + if (is_fifo) { + type += "_FIFO_"; + if (sync_fifo) + type += "SYNC_"; + else + type += "ASYNC_"; + } else + type += "_BRAM_"; + + if (split) { + type += stringf("A1_X%d_", width_for_mode(RMODE_A1_i)); + type += stringf("B1_X%d_", width_for_mode(RMODE_B1_i)); + type += stringf("A2_X%d_", width_for_mode(RMODE_A2_i)); + type += stringf("B2_X%d_", width_for_mode(RMODE_B2_i)); + type += "split"; + } else { + type += stringf("A_X%d_", width_for_mode(RMODE_A1_i)); + type += stringf("B_X%d_", width_for_mode(RMODE_B1_i)); + type += "nonsplit"; + } + + cell->type = RTLIL::escape_id(type); + log_debug("Changed type of memory cell %s to %s\n", log_id(cell->name), log_id(cell->type)); + } + } + + +} QlBramMergePass; + +PRIVATE_NAMESPACE_END \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/arith_map.v b/techlibs/quicklogic/qlf_k6n10f/arith_map.v index 908b17189..d39a3a19f 100644 --- a/techlibs/quicklogic/qlf_k6n10f/arith_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/arith_map.v @@ -56,43 +56,43 @@ module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); (* force_downto *) wire [Y_WIDTH-1:0] S = {AA ^ BB}; assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1]; - //assign CO[Y_WIDTH-1] = co; + //assign CO[Y_WIDTH-1] = co; generate - adder_carry intermediate_adder ( - .cin ( ), - .cout (C[0]), - .p (1'b0), - .g (CI), - .sumout () - ); + adder_carry intermediate_adder ( + .cin ( ), + .cout (C[0]), + .p (1'b0), + .g (CI), + .sumout () + ); endgenerate genvar i; generate if (Y_WIDTH > 2) begin for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice adder_carry my_adder ( - .cin(C[i]), - .g(AA[i]), - .p(S[i]), - .cout(C[i+1]), - .sumout(Y[i]) + .cin (C[i]), + .g (AA[i]), + .p (S[i]), + .cout (C[i+1]), + .sumout (Y[i]) ); - end + end end endgenerate generate - adder_carry final_adder ( - .cin (C[Y_WIDTH-2]), - .cout (), - .p (1'b0), - .g (1'b0), - .sumout (co) - ); + adder_carry final_adder ( + .cin (C[Y_WIDTH-2]), + .cout (), + .p (1'b0), + .g (1'b0), + .sumout (co) + ); endgenerate assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co; - assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; + assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1]; - assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; + assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; assign X = S; endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v index 3a06f676d..39e59d43f 100644 --- a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v @@ -1,73373 +1,73374 @@ // **AUTOGENERATED FILE** **DO NOT EDIT** -// Generated by qlf_k6n10f/generate_bram_types_sim.py at 2023-05-02 10:42:53.971682+00:00 +// Generated by generate_bram_types_sim.py at 2023-08-17 16:34:43.930013+00:00 +`timescale 1ns /10ps module TDP36K_BRAM_A_X1_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v index 7d04c5dda..43f5dc95e 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v @@ -15,27 +15,27 @@ // SPDX-License-Identifier: Apache-2.0 module BRAM2x18_SP ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -161,10 +161,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -190,12 +190,12 @@ localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -220,12 +220,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -250,12 +250,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -280,12 +280,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -344,49 +344,49 @@ assign WEN_B2_i = 1'b0; assign BE_B2_i = 4'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -442,44 +442,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module BRAM2x18_dP ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -487,7 +487,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -621,11 +621,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -661,12 +661,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -691,12 +691,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -721,12 +721,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -751,12 +751,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -837,93 +837,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -981,209 +981,209 @@ endmodule module BRAM2x18_SFIFO ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; - input CLK1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input CLK2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -1224,207 +1224,207 @@ endmodule module BRAM2x18_AFIFO ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; - input Push_Clk1, Pop_Clk1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input Push_Clk2, Pop_Clk2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_map.v index 42e1fc98b..82bbceeff 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_map.v @@ -15,15 +15,15 @@ // SPDX-License-Identifier: Apache-2.0 module RAM_36K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -130,7 +130,7 @@ wire [35:0] PORT_B_RDATA; wire [35:0] PORT_A_WDATA; wire [14:0] WR_ADDR_INT; -wire [14:0] RD_ADDR_INT; +wire [14:0] RD_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -156,12 +156,12 @@ assign PORT_A_CLK = WR_CLK_i; assign PORT_B_CLK = RD_CLK_i; generate - if (WR_ADDR_WIDTH == 15) begin - assign WR_ADDR_INT = WR_ADDR_i; - end else begin - assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; - assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; - end + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end endgenerate case (WR_DATA_WIDTH) @@ -189,12 +189,12 @@ case (WR_DATA_WIDTH) endcase generate - if (RD_ADDR_WIDTH == 15) begin - assign RD_ADDR_INT = RD_ADDR_i; - end else begin - assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; - assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; - end + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end endgenerate case (RD_DATA_WIDTH) @@ -240,17 +240,17 @@ assign WEN_B1_i = 1'b0; assign {BE_B2_i, BE_B1_i} = 4'h0; generate - if (WR_DATA_WIDTH == 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; @@ -260,15 +260,15 @@ assign WDATA_B1_i = 18'h0; assign WDATA_B2_i = 18'h0; generate - if (RD_DATA_WIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; @@ -326,15 +326,15 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module RAM_18K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -353,69 +353,69 @@ input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; input wire [WR_DATA_WIDTH-1 :0] WDATA_i; output wire [RD_DATA_WIDTH-1 :0] RDATA_o; - (* is_inferred = 0 *) - (* is_split = 0 *) - (* is_fifo = 0 *) - BRAM2x18_SP #( - .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), - .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .BE1_WIDTH(BE_WIDTH), - .WR2_ADDR_WIDTH(), - .RD2_ADDR_WIDTH(), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .BE2_WIDTH() - ) U1 - ( - .RESET_ni(1'b1), - - .WEN1_i(WEN_i), - .REN1_i(REN_i), - .WR1_CLK_i(WR_CLK_i), - .RD1_CLK_i(RD_CLK_i), - .WR1_BE_i(WR_BE_i), - .WR1_ADDR_i(WR_ADDR_i), - .RD1_ADDR_i(RD_ADDR_i), - .WDATA1_i(WDATA_i), - .RDATA1_o(RDATA_o), - - .WEN2_i(1'b0), - .REN2_i(1'b0), - .WR2_CLK_i(1'b0), - .RD2_CLK_i(1'b0), - .WR2_BE_i(2'b00), - .WR2_ADDR_i(14'h0), - .RD2_ADDR_i(14'h0), - .WDATA2_i(18'h0), - .RDATA2_o() - ); - + (* is_inferred = 0 *) + (* is_split = 0 *) + (* is_fifo = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + endmodule module RAM_18K_X2_BLK ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -541,10 +541,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -570,12 +570,12 @@ localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -600,12 +600,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -630,12 +630,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -660,12 +660,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -724,49 +724,49 @@ assign WEN_B2_i = 1'b0; assign BE_B2_i = 4'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -824,22 +824,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_36K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -956,7 +956,7 @@ wire [35:0] PORT_A_WDATA; wire [35:0] PORT_A_RDATA; wire [14:0] PORT_A_ADDR_INT; -wire [14:0] PORT_B_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -982,12 +982,12 @@ assign PORT_A_CLK = PORT_A_CLK_i; assign PORT_B_CLK = PORT_B_CLK_i; generate - if (PORT_A_AWIDTH == 15) begin - assign PORT_A_ADDR_INT = PORT_A_ADDR_i; - end else begin - assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; - assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; - end + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end endgenerate case (PORT_A_DWIDTH) @@ -1015,12 +1015,12 @@ case (PORT_A_DWIDTH) endcase generate - if (PORT_B_AWIDTH == 15) begin - assign PORT_B_ADDR_INT = PORT_B_ADDR_i; - end else begin - assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; - assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; - end + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end endgenerate case (PORT_B_DWIDTH) @@ -1076,63 +1076,63 @@ assign WEN_B1_i = PORT_B_WEN_i; assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; assign WDATA_A2_i = PORT_A_WDATA[35:18]; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end endgenerate assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; - assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; - end else begin - assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B_WDATA[17:0]; assign WDATA_B2_i = PORT_B_WDATA[35:18]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; @@ -1188,22 +1188,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -1248,80 +1248,80 @@ BRAM2x18_dP #( .PORT_B2_DWIDTH(), .PORT_B2_WR_BE_WIDTH() ) U1 ( - .PORT_A1_CLK_i(PORT_A_CLK_i), - .PORT_A1_WEN_i(PORT_A_WEN_i), - .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), - .PORT_A1_REN_i(PORT_A_REN_i), - .PORT_A1_ADDR_i(PORT_A_ADDR_i), - .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), - .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), - - .PORT_B1_CLK_i(PORT_B_CLK_i), - .PORT_B1_WEN_i(PORT_B_WEN_i), - .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), - .PORT_B1_REN_i(PORT_B_REN_i), - .PORT_B1_ADDR_i(PORT_B_ADDR_i), - .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), - .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), - - .PORT_A2_CLK_i(1'b0), - .PORT_A2_WEN_i(1'b0), - .PORT_A2_WR_BE_i(2'b00), - .PORT_A2_REN_i(1'b0), - .PORT_A2_ADDR_i(14'h0), - .PORT_A2_WR_DATA_i(18'h0), - .PORT_A2_RD_DATA_o(), - - .PORT_B2_CLK_i(1'b0), - .PORT_B2_WEN_i(1'b0), - .PORT_B2_WR_BE_i(2'b00), - .PORT_B2_REN_i(1'b0), - .PORT_B2_ADDR_i(14'h0), - .PORT_B2_WR_DATA_i(18'h0), - .PORT_B2_RD_DATA_o() + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() ); endmodule -module DPRAM_18K_X2_BLK ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -1329,7 +1329,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -1464,11 +1464,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -1504,12 +1504,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -1534,12 +1534,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -1564,12 +1564,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -1594,12 +1594,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -1680,93 +1680,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -1825,154 +1825,154 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module SFIFO_36K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - 32, 36: rwmode = 36; - default: rwmode = 36; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - - wire Push_Clk, Pop_Clk; - - assign Push_Clk = CLK; - assign Pop_Clk = CLK; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); - localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = PORT_A_WRWIDTH *) - (* port_b_dwidth = PORT_B_WRWIDTH *) - TDP36K _TECHMAP_REPLACE_ ( + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), .WDATA_A2_i(in_reg[35:18]), @@ -2008,155 +2008,155 @@ module SFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); - -endmodule + +endmodule module AFIFO_36K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - 32, 36: rwmode = 36; - default: rwmode = 36; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); - localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = PORT_A_WRWIDTH *) - (* port_b_dwidth = PORT_B_WRWIDTH *) + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), @@ -2193,292 +2193,292 @@ module AFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); - -endmodule + +endmodule module SFIFO_18K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_SFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .CLK1(CLK), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .CLK2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module SFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; - input CLK1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input CLK2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = PORT_A1_WRWIDTH *) - (* port_a2_dwidth = PORT_A2_WRWIDTH *) - (* port_b1_dwidth = PORT_B1_WRWIDTH *) - (* port_b2_dwidth = PORT_B2_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -2518,288 +2518,288 @@ module SFIFO_18K_X2_BLK ( endmodule module AFIFO_18K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_AFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .Push_Clk1(Push_Clk), - .Pop_Clk1(Pop_Clk), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .Push_Clk2(1'b0), - .Pop_Clk2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module AFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; - input Push_Clk1, Pop_Clk1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input Push_Clk2, Pop_Clk2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = PORT_A1_WRWIDTH *) - (* port_a2_dwidth = PORT_A2_WRWIDTH *) - (* port_b1_dwidth = PORT_B1_WRWIDTH *) - (* port_b2_dwidth = PORT_B2_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v index 2c2b814ab..5f04c0e7f 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v @@ -18,685 +18,685 @@ `default_nettype none module TDP36K ( - RESET_ni, - WEN_A1_i, - WEN_B1_i, - REN_A1_i, - REN_B1_i, - CLK_A1_i, - CLK_B1_i, - BE_A1_i, - BE_B1_i, - ADDR_A1_i, - ADDR_B1_i, - WDATA_A1_i, - WDATA_B1_i, - RDATA_A1_o, - RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, - WEN_B2_i, - REN_A2_i, - REN_B2_i, - CLK_A2_i, - CLK_B2_i, - BE_A2_i, - BE_B2_i, - ADDR_A2_i, - ADDR_B2_i, - WDATA_A2_i, - WDATA_B2_i, - RDATA_A2_o, - RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, + WEN_B1_i, + REN_A1_i, + REN_B1_i, + CLK_A1_i, + CLK_B1_i, + BE_A1_i, + BE_B1_i, + ADDR_A1_i, + ADDR_B1_i, + WDATA_A1_i, + WDATA_B1_i, + RDATA_A1_o, + RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, + WEN_B2_i, + REN_A2_i, + REN_B2_i, + CLK_A2_i, + CLK_B2_i, + BE_A2_i, + BE_B2_i, + ADDR_A2_i, + ADDR_B2_i, + WDATA_A2_i, + WDATA_B2_i, + RDATA_A2_o, + RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - // First 18K RAMFIFO (41 bits) - localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; - localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; - localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; - localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; - localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; - localparam [ 0:0] FMODE1_i = MODE_BITS[13]; - localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; - localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; - localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; - localparam [11:0] UPAE1_i = MODE_BITS[28:17]; - localparam [11:0] UPAF1_i = MODE_BITS[40:29]; + // First 18K RAMFIFO (41 bits) + localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; + localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; + localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; + localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; + localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; + localparam [ 0:0] FMODE1_i = MODE_BITS[13]; + localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; + localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; + localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; + localparam [11:0] UPAE1_i = MODE_BITS[28:17]; + localparam [11:0] UPAF1_i = MODE_BITS[40:29]; - // Second 18K RAMFIFO (39 bits) - localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; - localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; - localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; - localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; - localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; - localparam [ 0:0] FMODE2_i = MODE_BITS[54]; - localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; - localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; - localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; - localparam [10:0] UPAE2_i = MODE_BITS[68:58]; - localparam [10:0] UPAF2_i = MODE_BITS[79:69]; + // Second 18K RAMFIFO (39 bits) + localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; + localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; + localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; + localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; + localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; + localparam [ 0:0] FMODE2_i = MODE_BITS[54]; + localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; + localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; + localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; + localparam [10:0] UPAE2_i = MODE_BITS[68:58]; + localparam [10:0] UPAF2_i = MODE_BITS[79:69]; - // Split (1 bit) - localparam [ 0:0] SPLIT_i = MODE_BITS[80]; + // Split (1 bit) + localparam [ 0:0] SPLIT_i = MODE_BITS[80]; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - input wire RESET_ni; - input wire WEN_A1_i; - input wire WEN_B1_i; - input wire REN_A1_i; - input wire REN_B1_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - input wire [1:0] BE_A1_i; - input wire [1:0] BE_B1_i; - input wire [14:0] ADDR_A1_i; - input wire [14:0] ADDR_B1_i; - input wire [17:0] WDATA_A1_i; - input wire [17:0] WDATA_B1_i; - output reg [17:0] RDATA_A1_o; - output reg [17:0] RDATA_B1_o; - input wire FLUSH1_i; - input wire WEN_A2_i; - input wire WEN_B2_i; - input wire REN_A2_i; - input wire REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - input wire [1:0] BE_A2_i; - input wire [1:0] BE_B2_i; - input wire [13:0] ADDR_A2_i; - input wire [13:0] ADDR_B2_i; - input wire [17:0] WDATA_A2_i; - input wire [17:0] WDATA_B2_i; - output reg [17:0] RDATA_A2_o; - output reg [17:0] RDATA_B2_o; - input wire FLUSH2_i; - wire EMPTY2; - wire EPO2; - wire EWM2; - wire FULL2; - wire FMO2; - wire FWM2; - wire EMPTY1; - wire EPO1; - wire EWM1; - wire FULL1; - wire FMO1; - wire FWM1; - wire UNDERRUN1; - wire OVERRUN1; - wire UNDERRUN2; - wire OVERRUN2; - wire UNDERRUN3; - wire OVERRUN3; - wire EMPTY3; - wire EPO3; - wire EWM3; - wire FULL3; - wire FMO3; - wire FWM3; - wire ram_fmode1; - wire ram_fmode2; - wire [17:0] ram_rdata_a1; - wire [17:0] ram_rdata_b1; - wire [17:0] ram_rdata_a2; - wire [17:0] ram_rdata_b2; - reg [17:0] ram_wdata_a1; - reg [17:0] ram_wdata_b1; - reg [17:0] ram_wdata_a2; - reg [17:0] ram_wdata_b2; - reg [14:0] laddr_a1; - reg [14:0] laddr_b1; - wire [13:0] ram_addr_a1; - wire [13:0] ram_addr_b1; - wire [13:0] ram_addr_a2; - wire [13:0] ram_addr_b2; - wire smux_clk_a1; - wire smux_clk_b1; - wire smux_clk_a2; - wire smux_clk_b2; - reg [1:0] ram_be_a1; - reg [1:0] ram_be_a2; - reg [1:0] ram_be_b1; - reg [1:0] ram_be_b2; - wire [2:0] ram_rmode_a1; - wire [2:0] ram_wmode_a1; - wire [2:0] ram_rmode_b1; - wire [2:0] ram_wmode_b1; - wire [2:0] ram_rmode_a2; - wire [2:0] ram_wmode_a2; - wire [2:0] ram_rmode_b2; - wire [2:0] ram_wmode_b2; - wire ram_ren_a1; - wire ram_ren_b1; - wire ram_ren_a2; - wire ram_ren_b2; - wire ram_wen_a1; - wire ram_wen_b1; - wire ram_wen_a2; - wire ram_wen_b2; - wire ren_o; - wire [11:0] ff_raddr; - wire [11:0] ff_waddr; - reg [35:0] fifo_rdata; - wire [1:0] fifo_rmode; - wire [1:0] fifo_wmode; - wire [1:0] bwl; - wire [17:0] pl_dout0; - wire [17:0] pl_dout1; - wire sclk_a1; - wire sclk_b1; - wire sclk_a2; - wire sclk_b2; - wire sreset; - wire flush1; - wire flush2; - assign sreset = RESET_ni; - assign flush1 = ~FLUSH1_i; - assign flush2 = ~FLUSH2_i; - assign ram_fmode1 = FMODE1_i & SPLIT_i; - assign ram_fmode2 = FMODE2_i & SPLIT_i; - assign smux_clk_a1 = CLK_A1_i; - assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); - assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); - assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); - assign sclk_a1 = smux_clk_a1; - assign sclk_a2 = smux_clk_a2; - assign sclk_b1 = smux_clk_b1; - assign sclk_b2 = smux_clk_b2; - assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); - assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); - assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); - assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); - localparam MODE_36 = 3'b011; - assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); - assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); - assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); - assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); - assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); - assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); - assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); - assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); - assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); - localparam MODE_18 = 3'b010; - localparam MODE_9 = 3'b001; - always @(*) begin : WDATA_SEL - case (SPLIT_i) - 1: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A2_i; - ram_wdata_b1 = WDATA_B1_i; - ram_wdata_b2 = WDATA_B2_i; - ram_be_a2 = BE_A2_i; - ram_be_b2 = BE_B2_i; - ram_be_a1 = BE_A1_i; - ram_be_b1 = BE_B1_i; - end - 0: begin - case (WMODE_A1_i) - MODE_36: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A2_i; - ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); - ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); - end - MODE_18: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A1_i; - ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); - ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); - end - MODE_9: begin - ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; - ram_wdata_a1[16] = WDATA_A1_i[16]; - ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; - ram_wdata_a1[17] = WDATA_A1_i[16]; - ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; - ram_wdata_a2[16] = WDATA_A1_i[16]; - ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; - ram_wdata_a2[17] = WDATA_A1_i[16]; - case (bwl) - 0: {ram_be_a2, ram_be_a1} = 4'b0001; - 1: {ram_be_a2, ram_be_a1} = 4'b0010; - 2: {ram_be_a2, ram_be_a1} = 4'b0100; - 3: {ram_be_a2, ram_be_a1} = 4'b1000; - endcase - end - default: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A1_i; - ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); - ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); - end - endcase - case (WMODE_B1_i) - MODE_36: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); - ram_be_b2 = BE_B2_i; - ram_be_b1 = BE_B1_i; - end - MODE_18: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_be_b1 = BE_B1_i; - ram_be_b2 = BE_B1_i; - end - MODE_9: begin - ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; - ram_wdata_b1[16] = WDATA_B1_i[16]; - ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; - ram_wdata_b1[17] = WDATA_B1_i[16]; - ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; - ram_wdata_b2[16] = WDATA_B1_i[16]; - ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; - ram_wdata_b2[17] = WDATA_B1_i[16]; - case (ADDR_B1_i[4:3]) - 0: {ram_be_b2, ram_be_b1} = 4'b0001; - 1: {ram_be_b2, ram_be_b1} = 4'b0010; - 2: {ram_be_b2, ram_be_b1} = 4'b0100; - 3: {ram_be_b2, ram_be_b1} = 4'b1000; - endcase - end - default: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_be_b2 = BE_B1_i; - ram_be_b1 = BE_B1_i; - end - endcase - end - endcase - end - assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); - assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); - assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); - assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); - assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); - assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); - assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); - assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); - always @(*) begin : FIFO_READ_SEL - case (RMODE_B1_i) - MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; - MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); - MODE_9: - case (ff_raddr[1:0]) - 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; - 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; - 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; - 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; - endcase - default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; - endcase - end - localparam MODE_1 = 3'b101; - localparam MODE_2 = 3'b110; - localparam MODE_4 = 3'b100; - always @(*) begin : RDATA_SEL - case (SPLIT_i) - 1: begin - RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); - RDATA_B1_o = ram_rdata_b1; - RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); - RDATA_B2_o = ram_rdata_b2; - end - 0: begin - if (FMODE1_i) begin - RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; - RDATA_A2_o = 18'b000000000000000000; - end - else - case (RMODE_A1_i) - MODE_36: begin - RDATA_A1_o = {ram_rdata_a1[17:0]}; - RDATA_A2_o = {ram_rdata_a2[17:0]}; - end - MODE_18: begin - RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); - RDATA_A2_o = 18'b000000000000000000; - end - MODE_9: begin - RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); - RDATA_A2_o = 18'b000000000000000000; - end - MODE_4: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:4] = 14'b00000000000000; - RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); - end - MODE_2: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:2] = 16'b0000000000000000; - RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); - end - MODE_1: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:1] = 17'b00000000000000000; - RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); - end - default: begin - RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; - RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; - end - endcase - case (RMODE_B1_i) - MODE_36: begin - RDATA_B1_o = {ram_rdata_b1}; - RDATA_B2_o = {ram_rdata_b2}; - end - MODE_18: begin - RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); - RDATA_B2_o = 18'b000000000000000000; - end - MODE_9: begin - RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); - RDATA_B2_o = 18'b000000000000000000; - end - MODE_4: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:4] = 14'b00000000000000; - RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); - end - MODE_2: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:2] = 16'b0000000000000000; - RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); - end - MODE_1: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:1] = 17'b00000000000000000; - RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); - end - default: begin - RDATA_B1_o = ram_rdata_b1; - RDATA_B2_o = ram_rdata_b2; - end - endcase - end - endcase - end - always @(posedge sclk_a1 or negedge sreset) - if (sreset == 0) - laddr_a1 <= 1'sb0; - else - laddr_a1 <= ADDR_A1_i; - always @(posedge sclk_b1 or negedge sreset) - if (sreset == 0) - laddr_b1 <= 1'sb0; - else - laddr_b1 <= ADDR_B1_i; - assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); - assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); - fifo_ctl #( - .ADDR_WIDTH(12), - .FIFO_WIDTH(3'd4), - .DEPTH(7) - ) fifo36_ctl( - .rclk(sclk_b1), - .rst_R_n(flush1), - .wclk(sclk_a1), - .rst_W_n(flush1), - .ren(REN_B1_i), - .wen(ram_wen_a1), - .sync(SYNC_FIFO1_i), - .rmode(fifo_rmode), - .wmode(fifo_wmode), - .ren_o(ren_o), - .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), - .raddr(ff_raddr), - .waddr(ff_waddr), - .upaf(UPAF1_i), - .upae(UPAE1_i) - ); - TDP18K_FIFO #( - .UPAF_i(UPAF1_i[10:0]), - .UPAE_i(UPAE1_i[10:0]), - .SYNC_FIFO_i(SYNC_FIFO1_i), - .POWERDN_i(POWERDN1_i), - .SLEEP_i(SLEEP1_i), - .PROTECT_i(PROTECT1_i) - )u1( - .RMODE_A_i(ram_rmode_a1), - .RMODE_B_i(ram_rmode_b1), - .WMODE_A_i(ram_wmode_a1), - .WMODE_B_i(ram_wmode_b1), - .WEN_A_i(ram_wen_a1), - .WEN_B_i(ram_wen_b1), - .REN_A_i(ram_ren_a1), - .REN_B_i(ram_ren_b1), - .CLK_A_i(sclk_a1), - .CLK_B_i(sclk_b1), - .BE_A_i(ram_be_a1), - .BE_B_i(ram_be_b1), - .ADDR_A_i(ram_addr_a1), - .ADDR_B_i(ram_addr_b1), - .WDATA_A_i(ram_wdata_a1), - .WDATA_B_i(ram_wdata_b1), - .RDATA_A_o(ram_rdata_a1), - .RDATA_B_o(ram_rdata_b1), - .EMPTY_o(EMPTY1), - .EPO_o(EPO1), - .EWM_o(EWM1), - .UNDERRUN_o(UNDERRUN1), - .FULL_o(FULL1), - .FMO_o(FMO1), - .FWM_o(FWM1), - .OVERRUN_o(OVERRUN1), - .FLUSH_ni(flush1), - .FMODE_i(ram_fmode1) - ); - TDP18K_FIFO #( - .UPAF_i(UPAF2_i), - .UPAE_i(UPAE2_i), - .SYNC_FIFO_i(SYNC_FIFO2_i), - .POWERDN_i(POWERDN2_i), - .SLEEP_i(SLEEP2_i), - .PROTECT_i(PROTECT2_i) - )u2( - .RMODE_A_i(ram_rmode_a2), - .RMODE_B_i(ram_rmode_b2), - .WMODE_A_i(ram_wmode_a2), - .WMODE_B_i(ram_wmode_b2), - .WEN_A_i(ram_wen_a2), - .WEN_B_i(ram_wen_b2), - .REN_A_i(ram_ren_a2), - .REN_B_i(ram_ren_b2), - .CLK_A_i(sclk_a2), - .CLK_B_i(sclk_b2), - .BE_A_i(ram_be_a2), - .BE_B_i(ram_be_b2), - .ADDR_A_i(ram_addr_a2), - .ADDR_B_i(ram_addr_b2), - .WDATA_A_i(ram_wdata_a2), - .WDATA_B_i(ram_wdata_b2), - .RDATA_A_o(ram_rdata_a2), - .RDATA_B_o(ram_rdata_b2), - .EMPTY_o(EMPTY2), - .EPO_o(EPO2), - .EWM_o(EWM2), - .UNDERRUN_o(UNDERRUN2), - .FULL_o(FULL2), - .FMO_o(FMO2), - .FWM_o(FWM2), - .OVERRUN_o(OVERRUN2), - .FLUSH_ni(flush2), - .FMODE_i(ram_fmode2) - ); + input wire RESET_ni; + input wire WEN_A1_i; + input wire WEN_B1_i; + input wire REN_A1_i; + input wire REN_B1_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + input wire [1:0] BE_A1_i; + input wire [1:0] BE_B1_i; + input wire [14:0] ADDR_A1_i; + input wire [14:0] ADDR_B1_i; + input wire [17:0] WDATA_A1_i; + input wire [17:0] WDATA_B1_i; + output reg [17:0] RDATA_A1_o; + output reg [17:0] RDATA_B1_o; + input wire FLUSH1_i; + input wire WEN_A2_i; + input wire WEN_B2_i; + input wire REN_A2_i; + input wire REN_B2_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + input wire [1:0] BE_A2_i; + input wire [1:0] BE_B2_i; + input wire [13:0] ADDR_A2_i; + input wire [13:0] ADDR_B2_i; + input wire [17:0] WDATA_A2_i; + input wire [17:0] WDATA_B2_i; + output reg [17:0] RDATA_A2_o; + output reg [17:0] RDATA_B2_o; + input wire FLUSH2_i; + wire EMPTY2; + wire EPO2; + wire EWM2; + wire FULL2; + wire FMO2; + wire FWM2; + wire EMPTY1; + wire EPO1; + wire EWM1; + wire FULL1; + wire FMO1; + wire FWM1; + wire UNDERRUN1; + wire OVERRUN1; + wire UNDERRUN2; + wire OVERRUN2; + wire UNDERRUN3; + wire OVERRUN3; + wire EMPTY3; + wire EPO3; + wire EWM3; + wire FULL3; + wire FMO3; + wire FWM3; + wire ram_fmode1; + wire ram_fmode2; + wire [17:0] ram_rdata_a1; + wire [17:0] ram_rdata_b1; + wire [17:0] ram_rdata_a2; + wire [17:0] ram_rdata_b2; + reg [17:0] ram_wdata_a1; + reg [17:0] ram_wdata_b1; + reg [17:0] ram_wdata_a2; + reg [17:0] ram_wdata_b2; + reg [14:0] laddr_a1; + reg [14:0] laddr_b1; + wire [13:0] ram_addr_a1; + wire [13:0] ram_addr_b1; + wire [13:0] ram_addr_a2; + wire [13:0] ram_addr_b2; + wire smux_clk_a1; + wire smux_clk_b1; + wire smux_clk_a2; + wire smux_clk_b2; + reg [1:0] ram_be_a1; + reg [1:0] ram_be_a2; + reg [1:0] ram_be_b1; + reg [1:0] ram_be_b2; + wire [2:0] ram_rmode_a1; + wire [2:0] ram_wmode_a1; + wire [2:0] ram_rmode_b1; + wire [2:0] ram_wmode_b1; + wire [2:0] ram_rmode_a2; + wire [2:0] ram_wmode_a2; + wire [2:0] ram_rmode_b2; + wire [2:0] ram_wmode_b2; + wire ram_ren_a1; + wire ram_ren_b1; + wire ram_ren_a2; + wire ram_ren_b2; + wire ram_wen_a1; + wire ram_wen_b1; + wire ram_wen_a2; + wire ram_wen_b2; + wire ren_o; + wire [11:0] ff_raddr; + wire [11:0] ff_waddr; + reg [35:0] fifo_rdata; + wire [1:0] fifo_rmode; + wire [1:0] fifo_wmode; + wire [1:0] bwl; + wire [17:0] pl_dout0; + wire [17:0] pl_dout1; + wire sclk_a1; + wire sclk_b1; + wire sclk_a2; + wire sclk_b2; + wire sreset; + wire flush1; + wire flush2; + assign sreset = RESET_ni; + assign flush1 = ~FLUSH1_i; + assign flush2 = ~FLUSH2_i; + assign ram_fmode1 = FMODE1_i & SPLIT_i; + assign ram_fmode2 = FMODE2_i & SPLIT_i; + assign smux_clk_a1 = CLK_A1_i; + assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); + assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); + assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign sclk_a1 = smux_clk_a1; + assign sclk_a2 = smux_clk_a2; + assign sclk_b1 = smux_clk_b1; + assign sclk_b2 = smux_clk_b2; + assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); + assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); + localparam MODE_36 = 3'b011; + assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); + assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); + assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); + assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); + assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); + localparam MODE_18 = 3'b010; + localparam MODE_9 = 3'b001; + always @(*) begin : WDATA_SEL + case (SPLIT_i) + 1: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_wdata_b1 = WDATA_B1_i; + ram_wdata_b2 = WDATA_B2_i; + ram_be_a2 = BE_A2_i; + ram_be_b2 = BE_B2_i; + ram_be_a1 = BE_A1_i; + ram_be_b1 = BE_B1_i; + end + 0: begin + case (WMODE_A1_i) + MODE_36: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + MODE_18: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); + ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); + end + MODE_9: begin + ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a1[16] = WDATA_A1_i[16]; + ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a1[17] = WDATA_A1_i[16]; + ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a2[16] = WDATA_A1_i[16]; + ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a2[17] = WDATA_A1_i[16]; + case (bwl) + 0: {ram_be_a2, ram_be_a1} = 4'b0001; + 1: {ram_be_a2, ram_be_a1} = 4'b0010; + 2: {ram_be_a2, ram_be_a1} = 4'b0100; + 3: {ram_be_a2, ram_be_a1} = 4'b1000; + endcase + end + default: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + endcase + case (WMODE_B1_i) + MODE_36: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); + ram_be_b2 = BE_B2_i; + ram_be_b1 = BE_B1_i; + end + MODE_18: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b1 = BE_B1_i; + ram_be_b2 = BE_B1_i; + end + MODE_9: begin + ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b1[16] = WDATA_B1_i[16]; + ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b1[17] = WDATA_B1_i[16]; + ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b2[16] = WDATA_B1_i[16]; + ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b2[17] = WDATA_B1_i[16]; + case (ADDR_B1_i[4:3]) + 0: {ram_be_b2, ram_be_b1} = 4'b0001; + 1: {ram_be_b2, ram_be_b1} = 4'b0010; + 2: {ram_be_b2, ram_be_b1} = 4'b0100; + 3: {ram_be_b2, ram_be_b1} = 4'b1000; + endcase + end + default: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b2 = BE_B1_i; + ram_be_b1 = BE_B1_i; + end + endcase + end + endcase + end + assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + always @(*) begin : FIFO_READ_SEL + case (RMODE_B1_i) + MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; + MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); + MODE_9: + case (ff_raddr[1:0]) + 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; + 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; + 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; + 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; + endcase + default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; + endcase + end + localparam MODE_1 = 3'b101; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : RDATA_SEL + case (SPLIT_i) + 1: begin + RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); + RDATA_B1_o = ram_rdata_b1; + RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); + RDATA_B2_o = ram_rdata_b2; + end + 0: begin + if (FMODE1_i) begin + RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; + RDATA_A2_o = 18'b000000000000000000; + end + else + case (RMODE_A1_i) + MODE_36: begin + RDATA_A1_o = {ram_rdata_a1[17:0]}; + RDATA_A2_o = {ram_rdata_a2[17:0]}; + end + MODE_18: begin + RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:4] = 14'b00000000000000; + RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); + end + MODE_2: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:2] = 16'b0000000000000000; + RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); + end + MODE_1: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:1] = 17'b00000000000000000; + RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); + end + default: begin + RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; + RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; + end + endcase + case (RMODE_B1_i) + MODE_36: begin + RDATA_B1_o = {ram_rdata_b1}; + RDATA_B2_o = {ram_rdata_b2}; + end + MODE_18: begin + RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:4] = 14'b00000000000000; + RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); + end + MODE_2: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:2] = 16'b0000000000000000; + RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); + end + MODE_1: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:1] = 17'b00000000000000000; + RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); + end + default: begin + RDATA_B1_o = ram_rdata_b1; + RDATA_B2_o = ram_rdata_b2; + end + endcase + end + endcase + end + always @(posedge sclk_a1 or negedge sreset) + if (sreset == 0) + laddr_a1 <= 1'sb0; + else + laddr_a1 <= ADDR_A1_i; + always @(posedge sclk_b1 or negedge sreset) + if (sreset == 0) + laddr_b1 <= 1'sb0; + else + laddr_b1 <= ADDR_B1_i; + assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); + assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); + fifo_ctl #( + .ADDR_WIDTH(12), + .FIFO_WIDTH(3'd4), + .DEPTH(7) + ) fifo36_ctl( + .rclk(sclk_b1), + .rst_R_n(flush1), + .wclk(sclk_a1), + .rst_W_n(flush1), + .ren(REN_B1_i), + .wen(ram_wen_a1), + .sync(SYNC_FIFO1_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF1_i), + .upae(UPAE1_i) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF1_i[10:0]), + .UPAE_i(UPAE1_i[10:0]), + .SYNC_FIFO_i(SYNC_FIFO1_i), + .POWERDN_i(POWERDN1_i), + .SLEEP_i(SLEEP1_i), + .PROTECT_i(PROTECT1_i) + )u1( + .RMODE_A_i(ram_rmode_a1), + .RMODE_B_i(ram_rmode_b1), + .WMODE_A_i(ram_wmode_a1), + .WMODE_B_i(ram_wmode_b1), + .WEN_A_i(ram_wen_a1), + .WEN_B_i(ram_wen_b1), + .REN_A_i(ram_ren_a1), + .REN_B_i(ram_ren_b1), + .CLK_A_i(sclk_a1), + .CLK_B_i(sclk_b1), + .BE_A_i(ram_be_a1), + .BE_B_i(ram_be_b1), + .ADDR_A_i(ram_addr_a1), + .ADDR_B_i(ram_addr_b1), + .WDATA_A_i(ram_wdata_a1), + .WDATA_B_i(ram_wdata_b1), + .RDATA_A_o(ram_rdata_a1), + .RDATA_B_o(ram_rdata_b1), + .EMPTY_o(EMPTY1), + .EPO_o(EPO1), + .EWM_o(EWM1), + .UNDERRUN_o(UNDERRUN1), + .FULL_o(FULL1), + .FMO_o(FMO1), + .FWM_o(FWM1), + .OVERRUN_o(OVERRUN1), + .FLUSH_ni(flush1), + .FMODE_i(ram_fmode1) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF2_i), + .UPAE_i(UPAE2_i), + .SYNC_FIFO_i(SYNC_FIFO2_i), + .POWERDN_i(POWERDN2_i), + .SLEEP_i(SLEEP2_i), + .PROTECT_i(PROTECT2_i) + )u2( + .RMODE_A_i(ram_rmode_a2), + .RMODE_B_i(ram_rmode_b2), + .WMODE_A_i(ram_wmode_a2), + .WMODE_B_i(ram_wmode_b2), + .WEN_A_i(ram_wen_a2), + .WEN_B_i(ram_wen_b2), + .REN_A_i(ram_ren_a2), + .REN_B_i(ram_ren_b2), + .CLK_A_i(sclk_a2), + .CLK_B_i(sclk_b2), + .BE_A_i(ram_be_a2), + .BE_B_i(ram_be_b2), + .ADDR_A_i(ram_addr_a2), + .ADDR_B_i(ram_addr_b2), + .WDATA_A_i(ram_wdata_a2), + .WDATA_B_i(ram_wdata_b2), + .RDATA_A_o(ram_rdata_a2), + .RDATA_B_o(ram_rdata_b2), + .EMPTY_o(EMPTY2), + .EPO_o(EPO2), + .EWM_o(EWM2), + .UNDERRUN_o(UNDERRUN2), + .FULL_o(FULL2), + .FMO_o(FMO2), + .FWM_o(FWM2), + .OVERRUN_o(OVERRUN2), + .FLUSH_ni(flush2), + .FMODE_i(ram_fmode2) + ); endmodule module RAM_18K_X2_BLK ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -810,10 +810,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -834,12 +834,12 @@ localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -864,12 +864,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -894,12 +894,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -924,12 +924,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -982,55 +982,55 @@ assign BE_A2_i = WR2_BE; assign REN_B1_i = REN1_i; assign WEN_B1_i = 1'b0; -assign BE_B1_i = 4'h0; +assign BE_B1_i = 2'h0; assign REN_B2_i = REN2_i; assign WEN_B2_i = 1'b0; -assign BE_B2_i = 4'h0; +assign BE_B2_i = 2'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -1088,27 +1088,27 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module BRAM2x18_SP ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -1222,10 +1222,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -1246,12 +1246,12 @@ localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -1276,12 +1276,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -1306,12 +1306,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -1336,12 +1336,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -1394,55 +1394,55 @@ assign BE_A2_i = WR2_BE; assign REN_B1_i = REN1_i; assign WEN_B1_i = 1'b0; -assign BE_B1_i = 4'h0; +assign BE_B1_i = 2'h0; assign REN_B2_i = REN2_i; assign WEN_B2_i = 1'b0; -assign BE_B2_i = 4'h0; +assign BE_B2_i = 2'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -1498,15 +1498,15 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module RAM_18K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -1525,56 +1525,56 @@ input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; input wire [WR_DATA_WIDTH-1 :0] WDATA_i; output wire [RD_DATA_WIDTH-1 :0] RDATA_o; - (* is_inferred = 0 *) - (* is_split = 0 *) - BRAM2x18_SP #( - .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), - .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .BE1_WIDTH(BE_WIDTH), - .WR2_ADDR_WIDTH(), - .RD2_ADDR_WIDTH(), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .BE2_WIDTH() - ) U1 - ( - .RESET_ni(1'b1), - - .WEN1_i(WEN_i), - .REN1_i(REN_i), - .WR1_CLK_i(WR_CLK_i), - .RD1_CLK_i(RD_CLK_i), - .WR1_BE_i(WR_BE_i), - .WR1_ADDR_i(WR_ADDR_i), - .RD1_ADDR_i(RD_ADDR_i), - .WDATA1_i(WDATA_i), - .RDATA1_o(RDATA_o), - - .WEN2_i(1'b0), - .REN2_i(1'b0), - .WR2_CLK_i(1'b0), - .RD2_CLK_i(1'b0), - .WR2_BE_i(2'b00), - .WR2_ADDR_i(14'h0), - .RD2_ADDR_i(14'h0), - .WDATA2_i(18'h0), - .RDATA2_o() - ); - + (* is_inferred = 0 *) + (* is_split = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + endmodule module RAM_36K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -1668,7 +1668,7 @@ wire [35:0] PORT_B_RDATA; wire [35:0] PORT_A_WDATA; wire [14:0] WR_ADDR_INT; -wire [14:0] RD_ADDR_INT; +wire [14:0] RD_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -1691,12 +1691,12 @@ assign PORT_A_CLK = WR_CLK_i; assign PORT_B_CLK = RD_CLK_i; generate - if (WR_ADDR_WIDTH == 15) begin - assign WR_ADDR_INT = WR_ADDR_i; - end else begin - assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; - assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; - end + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end endgenerate case (WR_DATA_WIDTH) @@ -1724,12 +1724,12 @@ case (WR_DATA_WIDTH) endcase generate - if (RD_ADDR_WIDTH == 15) begin - assign RD_ADDR_INT = RD_ADDR_i; - end else begin - assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; - assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; - end + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end endgenerate case (RD_DATA_WIDTH) @@ -1775,17 +1775,17 @@ assign WEN_B1_i = 1'b0; assign {BE_B2_i, BE_B1_i} = 4'h0; generate - if (WR_DATA_WIDTH == 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; @@ -1795,15 +1795,15 @@ assign WDATA_B1_i = 18'h0; assign WDATA_B2_i = 18'h0; generate - if (RD_DATA_WIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; @@ -1859,44 +1859,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_X2_BLK ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -1904,7 +1904,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -2027,11 +2027,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -2062,12 +2062,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -2092,12 +2092,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -2122,12 +2122,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -2152,12 +2152,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -2238,93 +2238,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -2381,44 +2381,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module BRAM2x18_dP ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -2426,7 +2426,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -2548,11 +2548,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -2583,12 +2583,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -2613,12 +2613,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -2643,12 +2643,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -2673,12 +2673,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -2759,93 +2759,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -2900,22 +2900,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -2959,57 +2959,57 @@ BRAM2x18_dP #( .PORT_B2_DWIDTH(), .PORT_B2_WR_BE_WIDTH() ) U1 ( - .PORT_A1_CLK_i(PORT_A_CLK_i), - .PORT_A1_WEN_i(PORT_A_WEN_i), - .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), - .PORT_A1_REN_i(PORT_A_REN_i), - .PORT_A1_ADDR_i(PORT_A_ADDR_i), - .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), - .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), - - .PORT_B1_CLK_i(PORT_B_CLK_i), - .PORT_B1_WEN_i(PORT_B_WEN_i), - .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), - .PORT_B1_REN_i(PORT_B_REN_i), - .PORT_B1_ADDR_i(PORT_B_ADDR_i), - .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), - .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), - - .PORT_A2_CLK_i(1'b0), - .PORT_A2_WEN_i(1'b0), - .PORT_A2_WR_BE_i(2'b00), - .PORT_A2_REN_i(1'b0), - .PORT_A2_ADDR_i(14'h0), - .PORT_A2_WR_DATA_i(18'h0), - .PORT_A2_RD_DATA_o(), - - .PORT_B2_CLK_i(1'b0), - .PORT_B2_WEN_i(1'b0), - .PORT_B2_WR_BE_i(2'b00), - .PORT_B2_REN_i(1'b0), - .PORT_B2_ADDR_i(14'h0), - .PORT_B2_WR_DATA_i(18'h0), - .PORT_B2_RD_DATA_o() + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() ); endmodule -module DPRAM_36K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -3113,7 +3113,7 @@ wire [35:0] PORT_A_WDATA; wire [35:0] PORT_A_RDATA; wire [14:0] PORT_A_ADDR_INT; -wire [14:0] PORT_B_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -3136,12 +3136,12 @@ assign PORT_A_CLK = PORT_A_CLK_i; assign PORT_B_CLK = PORT_B_CLK_i; generate - if (PORT_A_AWIDTH == 15) begin - assign PORT_A_ADDR_INT = PORT_A_ADDR_i; - end else begin - assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; - assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; - end + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end endgenerate case (PORT_A_DWIDTH) @@ -3169,12 +3169,12 @@ case (PORT_A_DWIDTH) endcase generate - if (PORT_B_AWIDTH == 15) begin - assign PORT_B_ADDR_INT = PORT_B_ADDR_i; - end else begin - assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; - assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; - end + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end endgenerate case (PORT_B_DWIDTH) @@ -3230,63 +3230,63 @@ assign WEN_B1_i = PORT_B_WEN_i; assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; assign WDATA_A2_i = PORT_A_WDATA[35:18]; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end endgenerate assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; - assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; - end else begin - assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B_WDATA[17:0]; assign WDATA_B2_i = PORT_B_WDATA[35:18]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; @@ -3342,192 +3342,192 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module BRAM2x18_SFIFO ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; - input wire CLK1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire CLK2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = WR1_DATA_WIDTH *) - (* port_b_dwidth = RD1_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -3567,270 +3567,270 @@ module BRAM2x18_SFIFO ( endmodule module SFIFO_18K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_SFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .CLK1(CLK), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .CLK2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module SFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; - input wire CLK1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire CLK2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = WR1_DATA_WIDTH *) - (* port_a2_dwidth = WR2_DATA_WIDTH *) - (* port_b1_dwidth = RD1_DATA_WIDTH *) - (* port_b2_dwidth = RD2_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -3871,187 +3871,187 @@ endmodule module BRAM2x18_AFIFO ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; - input wire Push_Clk1, Pop_Clk1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire Push_Clk2, Pop_Clk2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = WR1_DATA_WIDTH *) - (* port_b_dwidth = RD1_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -4091,268 +4091,268 @@ module BRAM2x18_AFIFO ( endmodule module AFIFO_18K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_AFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .Push_Clk1(Push_Clk), - .Pop_Clk1(Pop_Clk), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .Push_Clk2(1'b0), - .Pop_Clk2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module AFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; - input wire Push_Clk1, Pop_Clk1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire Push_Clk2, Pop_Clk2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = WR1_DATA_WIDTH *) - (* port_a2_dwidth = WR2_DATA_WIDTH *) - (* port_b1_dwidth = RD1_DATA_WIDTH *) - (* port_b2_dwidth = RD2_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -4392,138 +4392,138 @@ module AFIFO_18K_X2_BLK ( endmodule module SFIFO_36K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - - wire Push_Clk, Pop_Clk; - - assign Push_Clk = CLK; - assign Pop_Clk = CLK; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = WR_DATA_WIDTH *) - (* port_b_dwidth = RD_DATA_WIDTH *) - TDP36K _TECHMAP_REPLACE_ ( + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), .WDATA_A2_i(in_reg[35:18]), @@ -4559,138 +4559,138 @@ module SFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); -endmodule +endmodule module AFIFO_36K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = WR_DATA_WIDTH *) - (* port_b_dwidth = RD_DATA_WIDTH *) + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), @@ -4727,97 +4727,97 @@ module AFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); -endmodule +endmodule //=============================================================================== module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -4826,27 +4826,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -4858,93 +4858,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -4953,27 +4953,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -4985,93 +4985,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5080,27 +5080,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5112,93 +5112,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5207,27 +5207,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5239,93 +5239,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5334,27 +5334,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5366,93 +5366,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5461,27 +5461,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5493,93 +5493,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5588,27 +5588,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5620,93 +5620,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5715,27 +5715,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5747,93 +5747,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5842,27 +5842,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5874,93 +5874,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5969,27 +5969,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6001,93 +6001,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6096,27 +6096,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6128,93 +6128,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6223,27 +6223,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6255,93 +6255,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6350,27 +6350,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6382,93 +6382,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6477,27 +6477,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6509,93 +6509,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6604,27 +6604,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6636,93 +6636,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6731,27 +6731,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6763,93 +6763,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6858,27 +6858,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6890,93 +6890,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6985,27 +6985,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7017,93 +7017,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7112,27 +7112,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7144,93 +7144,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7239,27 +7239,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7271,93 +7271,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7366,27 +7366,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7398,93 +7398,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7493,27 +7493,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7525,93 +7525,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7620,27 +7620,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7652,93 +7652,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7747,27 +7747,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7779,93 +7779,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7874,27 +7874,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7906,93 +7906,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8001,27 +8001,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8033,93 +8033,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8128,27 +8128,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8160,93 +8160,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8255,27 +8255,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8287,93 +8287,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8382,27 +8382,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8414,93 +8414,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8509,27 +8509,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8541,93 +8541,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8636,27 +8636,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8668,93 +8668,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8763,27 +8763,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8795,93 +8795,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8890,27 +8890,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8922,93 +8922,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9017,27 +9017,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9049,93 +9049,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9144,27 +9144,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9176,93 +9176,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9271,27 +9271,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9303,93 +9303,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9398,27 +9398,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9430,93 +9430,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9525,27 +9525,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9557,93 +9557,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9652,27 +9652,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9684,93 +9684,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9779,27 +9779,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9811,93 +9811,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9906,27 +9906,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9938,93 +9938,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10033,27 +10033,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10065,93 +10065,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10160,27 +10160,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10192,93 +10192,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10287,27 +10287,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10319,93 +10319,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10414,27 +10414,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10446,93 +10446,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10541,27 +10541,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10573,93 +10573,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10668,27 +10668,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10700,93 +10700,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10795,27 +10795,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10827,93 +10827,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10922,27 +10922,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10954,93 +10954,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; + parameter [80:0] MODE_BITS = 81'd0; - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; - input wire FLUSH1_i; + input wire FLUSH1_i; - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; - input wire FLUSH2_i; + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -11049,27 +11049,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); diff --git a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v index 645a62f83..b9f406256 100644 --- a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v @@ -19,104 +19,104 @@ `default_nettype none (* abc9_lut=1 *) module LUT1(output wire O, input wire I0); - parameter [1:0] INIT = 0; - assign O = I0 ? INIT[1] : INIT[0]; - specify - (I0 => O) = 74; - endspecify + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; + specify + (I0 => O) = 74; + endspecify endmodule (* abc9_lut=2 *) module LUT2(output wire O, input wire I0, I1); - parameter [3:0] INIT = 0; - wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 116; - (I1 => O) = 74; - endspecify + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 116; + (I1 => O) = 74; + endspecify endmodule (* abc9_lut=3 *) module LUT3(output wire O, input wire I0, I1, I2); - parameter [7:0] INIT = 0; - wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 162; - (I1 => O) = 116; - (I2 => O) = 174; - endspecify + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 162; + (I1 => O) = 116; + (I2 => O) = 174; + endspecify endmodule (* abc9_lut=3 *) module LUT4(output wire O, input wire I0, I1, I2, I3); - parameter [15:0] INIT = 0; - wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 201; - (I1 => O) = 162; - (I2 => O) = 116; - (I3 => O) = 74; - endspecify + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 201; + (I1 => O) = 162; + (I2 => O) = 116; + (I3 => O) = 74; + endspecify endmodule (* abc9_lut=3 *) module LUT5(output wire O, input wire I0, I1, I2, I3, I4); - parameter [31:0] INIT = 0; - wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; - wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 228; - (I1 => O) = 189; - (I2 => O) = 143; - (I3 => O) = 100; - (I4 => O) = 55; - endspecify + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 228; + (I1 => O) = 189; + (I2 => O) = 143; + (I3 => O) = 100; + (I4 => O) = 55; + endspecify endmodule (* abc9_lut=5 *) module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5); - parameter [63:0] INIT = 0; - wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; - wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; - wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 251; - (I1 => O) = 212; - (I2 => O) = 166; - (I3 => O) = 123; - (I4 => O) = 77; - (I5 => O) = 43; - endspecify + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 251; + (I1 => O) = 212; + (I2 => O) = 166; + (I3 => O) = 123; + (I4 => O) = 77; + (I5 => O) = 43; + endspecify endmodule (* abc9_flop, lib_whitebox *) module sh_dff( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; - always @(posedge C) - Q <= D; - - specify - (posedge C => (Q +: D)) = 0; - $setuphold(posedge C, D, 0, 0); - endspecify + initial Q = 1'b0; + always @(posedge C) + Q <= D; + + specify + (posedge C => (Q +: D)) = 0; + $setuphold(posedge C, D, 0, 0); + endspecify endmodule @@ -124,253 +124,253 @@ endmodule (* blackbox *) (* keep *) module adder_carry( - output wire sumout, - (* abc9_carry *) - output wire cout, - input wire p, - input wire g, - (* abc9_carry *) - input wire cin + output wire sumout, + (* abc9_carry *) + output wire cout, + input wire p, + input wire g, + (* abc9_carry *) + input wire cin ); - assign sumout = p ^ cin; - assign cout = p ? cin : g; - - specify - (p => sumout) = 35; - (g => sumout) = 35; - (cin => sumout) = 40; - (p => cout) = 67; - (g => cout) = 65; - (cin => cout) = 69; - endspecify + assign sumout = p ^ cin; + assign cout = p ? cin : g; + + specify + (p => sumout) = 35; + (g => sumout) = 35; + (cin => sumout) = 40; + (p => cout) = 67; + (g => cout) = 65; + (cin => cout) = 69; + endspecify endmodule (* abc9_flop, lib_whitebox *) module dff( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @(posedge C) - Q <= D; + always @(posedge C) + Q <= D; - specify - (posedge C=>(Q+:D)) = 285; - $setuphold(posedge C, D, 56, 0); - endspecify + specify + (posedge C=>(Q+:D)) = 285; + $setuphold(posedge C, D, 56, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffn( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @(negedge C) - Q <= D; - - specify - (negedge C=>(Q+:D)) = 285; - $setuphold(negedge C, D, 56, 0); - endspecify + always @(negedge C) + Q <= D; + + specify + (negedge C=>(Q+:D)) = 285; + $setuphold(negedge C, D, 56, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @(posedge C or negedge S or negedge R) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; + always @(posedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; - specify - (posedge C => (Q +: D)) = 280; - (R => Q) = 0; - (S => Q) = 0; - $setuphold(posedge C, D, 56, 0); - $setuphold(posedge C, E, 32, 0); - $setuphold(posedge C, R, 0, 0); - $setuphold(posedge C, S, 0, 0); - $recrem(posedge R, posedge C, 0, 0); - $recrem(posedge S, posedge C, 0, 0); - endspecify + specify + (posedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, E, 32, 0); + $setuphold(posedge C, R, 0, 0); + $setuphold(posedge C, S, 0, 0); + $recrem(posedge R, posedge C, 0, 0); + $recrem(posedge S, posedge C, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffnsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @(negedge C or negedge S or negedge R) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (negedge C => (Q +: D)) = 280; - (R => Q) = 0; - (S => Q) = 0; - $setuphold(negedge C, D, 56, 0); - $setuphold(negedge C, E, 32, 0); - $setuphold(negedge C, R, 0, 0); - $setuphold(negedge C, S, 0, 0); - $recrem(posedge R, negedge C, 0, 0); - $recrem(posedge S, negedge C, 0, 0); - endspecify + always @(negedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, E, 32, 0); + $setuphold(negedge C, R, 0, 0); + $setuphold(negedge C, S, 0, 0); + $recrem(posedge R, negedge C, 0, 0); + $recrem(posedge S, negedge C, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module sdffsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @(posedge C) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (posedge C => (Q +: D)) = 280; - $setuphold(posedge C, D, 56, 0); - $setuphold(posedge C, R, 32, 0); - $setuphold(posedge C, S, 0, 0); - $setuphold(posedge C, E, 0, 0); - endspecify + always @(posedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, R, 32, 0); + $setuphold(posedge C, S, 0, 0); + $setuphold(posedge C, E, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module sdffnsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @(negedge C) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (negedge C => (Q +: D)) = 280; - $setuphold(negedge C, D, 56, 0); - $setuphold(negedge C, R, 32, 0); - $setuphold(negedge C, S, 0, 0); - $setuphold(negedge C, E, 0, 0); - endspecify + always @(negedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, R, 32, 0); + $setuphold(negedge C, S, 0, 0); + $setuphold(negedge C, E, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module latchsre ( - output reg Q, - input wire S, - input wire R, - input wire D, - input wire G, - input wire E + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @* - begin - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E && G) - Q <= D; - end - - specify - (posedge G => (Q +: D)) = 0; - $setuphold(posedge G, D, 0, 0); - $setuphold(posedge G, E, 0, 0); - $setuphold(posedge G, R, 0, 0); - $setuphold(posedge G, S, 0, 0); - endspecify + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && G) + Q <= D; + end + + specify + (posedge G => (Q +: D)) = 0; + $setuphold(posedge G, D, 0, 0); + $setuphold(posedge G, E, 0, 0); + $setuphold(posedge G, R, 0, 0); + $setuphold(posedge G, S, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module latchnsre ( - output reg Q, - input wire S, - input wire R, - input wire D, - input wire G, - input wire E + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @* - begin - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E && !G) - Q <= D; - end - - specify - (negedge G => (Q +: D)) = 0; - $setuphold(negedge G, D, 0, 0); - $setuphold(negedge G, E, 0, 0); - $setuphold(negedge G, R, 0, 0); - $setuphold(negedge G, S, 0, 0); - endspecify + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && !G) + Q <= D; + end + + specify + (negedge G => (Q +: D)) = 0; + $setuphold(negedge G, D, 0, 0); + $setuphold(negedge G, E, 0, 0); + $setuphold(negedge G, R, 0, 0); + $setuphold(negedge G, S, 0, 0); + endspecify endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/ffs_map.v b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v index 26fa6ed36..43a71b425 100644 --- a/techlibs/quicklogic/qlf_k6n10f/ffs_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v @@ -16,116 +16,116 @@ // DFF, asynchronous set/reset, enable module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q); - input C; - input S; - input R; - input E; - input D; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); + input C; + input S; + input R; + input E; + input D; + output Q; + dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); endmodule module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q); - input C; - input S; - input R; - input E; - input D; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); + input C; + input S; + input R; + input E; + input D; + output Q; + dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); endmodule // DFF, synchronous set or reset, enable module \$_SDFFE_PN0P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); endmodule module \$_SDFFE_PN1P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); endmodule module \$_SDFFE_NN0P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); endmodule module \$_SDFFE_NN1P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); endmodule // Latch, no set/reset, no enable module \$_DLATCH_P_ (input E, D, output Q); - latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); endmodule module \$_DLATCH_N_ (input E, D, output Q); - latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); endmodule // Latch with async set and reset and enable module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q); - latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); endmodule module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q); - latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); endmodule module \$__SHREG_DFF_P_ (D, Q, C); - input D; - input C; - output Q; + input D; + input C; + output Q; - parameter DEPTH = 2; + parameter DEPTH = 2; - reg [DEPTH-2:0] q; + reg [DEPTH-2:0] q; - genvar i; - generate for (i = 0; i < DEPTH; i = i + 1) begin: slice + genvar i; + generate for (i = 0; i < DEPTH; i = i + 1) begin: slice - // First in chain - generate if (i == 0) begin - sh_dff #() shreg_beg ( - .Q(q[i]), - .D(D), - .C(C) - ); - end endgenerate - // Middle in chain - generate if (i > 0 && i != DEPTH-1) begin - sh_dff #() shreg_mid ( - .Q(q[i]), - .D(q[i-1]), - .C(C) - ); - end endgenerate - // Last in chain - generate if (i == DEPTH-1) begin - sh_dff #() shreg_end ( - .Q(Q), - .D(q[i-1]), - .C(C) - ); - end endgenerate + // First in chain + generate if (i == 0) begin + sh_dff #() shreg_beg ( + .Q(q[i]), + .D(D), + .C(C) + ); + end endgenerate + // Middle in chain + generate if (i > 0 && i != DEPTH-1) begin + sh_dff #() shreg_mid ( + .Q(q[i]), + .D(q[i-1]), + .C(C) + ); + end endgenerate + // Last in chain + generate if (i == DEPTH-1) begin + sh_dff #() shreg_end ( + .Q(Q), + .D(q[i-1]), + .C(C) + ); + end endgenerate end: slice endgenerate diff --git a/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py new file mode 100644 index 000000000..5f7da9097 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py @@ -0,0 +1,246 @@ +import sys +from datetime import datetime, timezone + +def generate(filename): + with open(filename, "w") as f: + f.write("// **AUTOGENERATED FILE** **DO NOT EDIT**\n") + f.write(f"// Generated by {sys.argv[0]} at {datetime.now(timezone.utc)}\n") + + f.write("`timescale 1ns /10ps\n") + for a_width in [1,2,4,9,18,36]: + for b_width in [1,2,4,9,18,36]: + f.write(f""" +module TDP36K_BRAM_A_X{a_width}_B_X{b_width}_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule +""") + + for a1_width in [1,2,4,9,18]: + for b1_width in [1,2,4,9,18]: + for a2_width in [1,2,4,9,18]: + for b2_width in [1,2,4,9,18]: + f.write(f""" +module TDP36K_BRAM_A1_X{a1_width}_B1_X{b1_width}_A2_X{a2_width}_B2_X{b2_width}_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule +""") + +if __name__ == "__main__": + filename = "bram_types_sim.v" + if len(sys.argv) > 1: + filename = sys.argv[1] + generate(filename) diff --git a/techlibs/quicklogic/quicklogic_eqn.cc b/techlibs/quicklogic/quicklogic_eqn.cc deleted file mode 100644 index b82a1b286..000000000 --- a/techlibs/quicklogic/quicklogic_eqn.cc +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2020-2022 F4PGA Authors - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include "kernel/sigtools.h" -#include "kernel/yosys.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct QuicklogicEqnPass : public Pass { - QuicklogicEqnPass() : Pass("quicklogic_eqn", "Quicklogic: Calculate equations for luts") {} - void help() override - { - log("\n"); - log(" quicklogic_eqn [selection]\n"); - log("\n"); - log("Calculate equations for luts since bitstream generator depends on it.\n"); - log("\n"); - } - - Const init2eqn(Const init, int inputs) - { - std::string init_bits = init.as_string(); - const char *names[] = {"I0", "I1", "I2", "I3", "I4"}; - - std::string eqn; - int width = (int)pow(2, inputs); - for (int i = 0; i < width; i++) { - if (init_bits[width - 1 - i] == '1') { - eqn += "("; - for (int j = 0; j < inputs; j++) { - if (i & (1 << j)) - eqn += names[j]; - else - eqn += std::string("~") + names[j]; - - if (j != (inputs - 1)) - eqn += "*"; - } - eqn += ")+"; - } - } - if (eqn.empty()) - return Const("0"); - eqn = eqn.substr(0, eqn.length() - 1); - return Const(eqn); - } - - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing Quicklogic_EQN pass (calculate equations for luts).\n"); - - extra_args(args, args.size(), design); - - int cnt = 0; - for (auto module : design->selected_modules()) { - for (auto cell : module->selected_cells()) { - if (cell->type == ID(LUT1)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 1)); - cnt++; - } - if (cell->type == ID(LUT2)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 2)); - cnt++; - } - if (cell->type == ID(LUT3)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 3)); - cnt++; - } - if (cell->type == ID(LUT4)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 4)); - cnt++; - } - if (cell->type == ID(LUT5)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 5)); - cnt++; - } - } - } - log_header(design, "Updated %d of LUT* elements with equation.\n", cnt); - } -} QuicklogicEqnPass; - -PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 15ab68a3f..d2df6bcff 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -129,10 +129,6 @@ struct SynthQuickLogicPass : public ScriptPass { blif_file = args[++argidx]; continue; } - if (args[argidx] == "-edif" && argidx + 1 < args.size()) { - edif_file = args[++argidx]; - continue; - } if (args[argidx] == "-verilog" && argidx+1 < args.size()) { verilog_file = args[++argidx]; continue; @@ -141,15 +137,15 @@ struct SynthQuickLogicPass : public ScriptPass { abc9 = false; continue; } - if (args[argidx] == "-nocarry") { + if (args[argidx] == "-nocarry" || args[argidx] == "-no_adder") { inferAdder = false; continue; } - if (args[argidx] == "-nobram") { + if (args[argidx] == "-nobram" || args[argidx] == "-no_bram") { nobram = true; continue; } - if (args[argidx] == "-bramtypes") { + if (args[argidx] == "-bramtypes" || args[argidx] == "-bram_types") { bramTypes = true; continue; } @@ -230,61 +226,8 @@ struct SynthQuickLogicPass : public ScriptPass { run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); run("techmap -map " + lib_path + family + "/brams_final_map.v"); - if (help_mode) { - run("chtype -set TDP36K_ t:TDP36K a:", "(if -bram_types)"); - } - else if (bramTypes) { - for (int a_dwidth : {1, 2, 4, 9, 18, 36}) - for (int b_dwidth: {1, 2, 4, 9, 18, 36}) { - run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_ASYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=1 %%i a:sync_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_SYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=1 %%i a:sync_fifo=1 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - } - - for (int a1_dwidth : {1, 2, 4, 9, 18}) - for (int b1_dwidth: {1, 2, 4, 9, 18}) - for (int a2_dwidth : {1, 2, 4, 9, 18}) - for (int b2_dwidth: {1, 2, 4, 9, 18}) { - run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=0 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_ASYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=0 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_SYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=1 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - } - - - for (int a_width : {1, 2, 4, 9, 18, 36}) - for (int b_width: {1, 2, 4, 9, 18, 36}) { - run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=1 %%i " - "a:port_a_width=%d %%i a:port_b_width=%d %%i", - a_width, b_width, a_width, b_width)); - } - - for (int a1_width : {1, 2, 4, 9, 18}) - for (int b1_width: {1, 2, 4, 9, 18}) - for (int a2_width : {1, 2, 4, 9, 18}) - for (int b2_width: {1, 2, 4, 9, 18}) { - run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=1 %%i " - "a:port_a1_width=%d %%i a:port_b1_width=%d %%i a:port_a2_width=%d %%i a:port_b2_width=%d %%i", - a1_width, b1_width, a2_width, b2_width, a1_width, b1_width, a2_width, b2_width)); - } + if (help_mode || bramTypes) { + run("ql_bram_types"); } } @@ -393,13 +336,6 @@ struct SynthQuickLogicPass : public ScriptPass { run(stringf("write_verilog -noattr -nohex %s", help_mode ? "" : verilog_file.c_str())); } } - - if (check_label("edif", "(if -edif)")) { - if (!edif_file.empty() || help_mode) { - run("splitnets -ports -format ()"); - run(stringf("write_edif -nogndvcc -attrprop -pvector par %s %s", top_opt.c_str(), edif_file.c_str())); - } - } } } SynthQuicklogicPass;