mirror of https://github.com/YosysHQ/yosys.git
RST -> RSTBRST for RAMB8BWER
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@ -52,7 +52,7 @@ module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
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.CLKBRDCLK(CLK2 ^ !CLKPOL2),
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.CLKBRDCLK(CLK2 ^ !CLKPOL2),
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.ENBRDEN(A1EN),
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.ENBRDEN(A1EN),
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.REGCEBREGCE(|1),
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.REGCEBREGCE(|1),
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.RSTB(|0)
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.RSTBRST(|0)
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);
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);
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endmodule
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endmodule
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@ -217,7 +217,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
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.CLKBRDCLK(CLK3 ^ !CLKPOL3),
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.CLKBRDCLK(CLK3 ^ !CLKPOL3),
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.ENBRDEN(|1),
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.ENBRDEN(|1),
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.REGCEBREGCE(|0),
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.REGCEBREGCE(|0),
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.RSTB(|0),
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.RSTBRST(|0),
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.WEBWEU(B1EN_2)
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.WEBWEU(B1EN_2)
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);
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);
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end else begin
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end else begin
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@ -248,7 +248,7 @@ module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DAT
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.CLKBRDCLK(CLK3 ^ !CLKPOL3),
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.CLKBRDCLK(CLK3 ^ !CLKPOL3),
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.ENBRDEN(|1),
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.ENBRDEN(|1),
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.REGCEBREGCE(|0),
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.REGCEBREGCE(|0),
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.RSTB(|0),
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.RSTBRST(|0),
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.WEBWEU(B1EN_2)
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.WEBWEU(B1EN_2)
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);
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);
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end endgenerate
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end endgenerate
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