riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

simplemap: Map `$xnor` to `$_XNOR_` cells 

The previous mapping to `$_XOR_` and `$_NOT_` predates the addition of
the `$_XNOR_` cell.
This commit is contained in:
Jannis Harder 2022-11-02 17:45:46 +01:00
parent f9db7c0599
commit 661fa5ff92
3 changed files with 5 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
passes/techmap/simplemap.cc
View File

@ -61,25 +61,11 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool()); sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool()); sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
if (cell->type == ID($xnor))
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_t[i]);
gate->setPort(ID::Y, sig_y[i]);
}
sig_y = sig_t;
}
IdString gate_type; IdString gate_type;
if (cell->type == ID($and)) gate_type = ID($_AND_); if (cell->type == ID($and)) gate_type = ID($_AND_);
if (cell->type == ID($or)) gate_type = ID($_OR_); if (cell->type == ID($or)) gate_type = ID($_OR_);
if (cell->type == ID($xor)) gate_type = ID($_XOR_); if (cell->type == ID($xor)) gate_type = ID($_XOR_);
if (cell->type == ID($xnor)) gate_type = ID($_XOR_); if (cell->type == ID($xnor)) gate_type = ID($_XNOR_);
log_assert(!gate_type.empty()); log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) { for (int i = 0; i < GetSize(sig_y); i++) {

2
tests/opt/opt_expr_xnor.ys
View File

@ -32,7 +32,7 @@ select -assert-count 1 c:*
cd fine_keepdc cd fine_keepdc
simplemap simplemap
opt_expr -keepdc opt_expr -keepdc
select -assert-count 1 t:$_XOR_ select -assert-count 1 t:$_XNOR_
cd cd
miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3

7
tests/opt/opt_expr_xor.ys
View File

@ -22,9 +22,8 @@ simplemap
equiv_opt -assert opt_expr equiv_opt -assert opt_expr
design -load postopt design -load postopt
select -assert-none t:$_XOR_ select -assert-none t:$_XOR_
select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ select -assert-none t:$_XNOR_
select -assert-count 3 t:$_NOT_ select -assert-count 2 t:$_NOT_
design -reset design -reset
read_verilog -icells <<EOT read_verilog -icells <<EOT
@ -36,7 +35,7 @@ EOT
select -assert-count 2 t:$_XNOR_ select -assert-count 2 t:$_XNOR_
equiv_opt -assert opt_expr equiv_opt -assert opt_expr
design -load postopt design -load postopt
select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ select -assert-none t:$_XNOR_
select -assert-count 1 t:$_NOT_ select -assert-count 1 t:$_NOT_