Merge pull request #38 from rubund/master

Corrected spelling mistakes found by lintian

Makefile

@@ -45,7 +45,7 @@ else
 endif
 
 YOSYS_VER := 0.3.0+
-GIT_REV := $(shell git rev-parse --short HEAD 2> /dev/null || echo UNKOWN)
+GIT_REV := $(shell git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 
 # set 'ABCREV = default' to use abc/ as it is

backends/blif/blif.cc

@@ -280,7 +280,7 @@ struct BlifBackend : public Backend {
 		log("    -false <cell-type> <out-port>\n");
 		log("        use the specified cell types to drive nets that are constant 1 or 0\n");
 		log("\n");
-		log("The following options can be usefull when the generated file is not going to be\n");
+		log("The following options can be useful when the generated file is not going to be\n");
 		log("read by a BLIF parser but a custom tool. It is recommended to not name the output\n");
 		log("file *.blif when any of this options is used.\n");
 		log("\n");

frontends/ast/simplify.cc

@@ -464,7 +464,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_DEFPARAM && !str.empty()) {
 		size_t pos = str.rfind('.');
 		if (pos == std::string::npos)
-			log_error("Defparam `%s' does not contain a dot (module/parameter seperator) at %s:%d!\n",
+			log_error("Defparam `%s' does not contain a dot (module/parameter separator) at %s:%d!\n",
 					RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
 		std::string modname = str.substr(0, pos), paraname = "\\" + str.substr(pos+1);
 		if (current_scope.count(modname) == 0 || current_scope.at(modname)->type != AST_CELL)

frontends/verific/build_amd64.txt

@@ -17,7 +17,7 @@ VERIFIC_DIR = /usr/local/src/verific_lib_eval
 --snap--
 
 
-2.) Install the neccessary multilib packages
+2.) Install the necessary multilib packages
 
 Hint: On debian/ubuntu the multilib packages have names such as
 libreadline-dev:amd64 or lib32readline6-dev, depending on the

frontends/verific/verific.cc

@@ -887,7 +887,7 @@ struct VerificPass : public Pass {
 			}
 
 			if (argidx > args.size() && args[argidx].substr(0, 1) == "-")
-				cmd_error(args, argidx, "unkown option");
+				cmd_error(args, argidx, "unknown option");
 
 			if (mode_all)
 			{

frontends/vhdl2verilog/vhdl2verilog.cc

@@ -116,7 +116,7 @@ struct Vhdl2verilogPass : public Pass {
 		if (argidx == args.size())
 			cmd_error(args, argidx, "Missing filenames.");
 		if (args[argidx].substr(0, 1) == "-")
-			cmd_error(args, argidx, "Unkown option.");
+			cmd_error(args, argidx, "Unknown option.");
 		if (top_entity.empty())
 			log_cmd_error("Missing -top option.\n");
 

kernel/register.cc

@@ -132,7 +132,7 @@ void Pass::extra_args(std::vector<std::string> args, size_t argidx, RTLIL::Desig
 		std::string arg = args[argidx];
 
 		if (arg.substr(0, 1) == "-")
-			cmd_error(args, argidx, "Unkown option or option in arguments.");
+			cmd_error(args, argidx, "Unknown option or option in arguments.");
 
 		if (!select)
 			cmd_error(args, argidx, "Extra argument.");
@@ -309,7 +309,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
 		std::string arg = args[argidx];
 
 		if (arg.substr(0, 1) == "-")
-			cmd_error(args, argidx, "Unkown option or option in arguments.");
+			cmd_error(args, argidx, "Unknown option or option in arguments.");
 		if (f != NULL)
 			cmd_error(args, argidx, "Extra filename argument in direct file mode.");
 
@@ -445,7 +445,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vector<st
 		std::string arg = args[argidx];
 
 		if (arg.substr(0, 1) == "-" && arg != "-")
-			cmd_error(args, argidx, "Unkown option or option in arguments.");
+			cmd_error(args, argidx, "Unknown option or option in arguments.");
 		if (f != NULL)
 			cmd_error(args, argidx, "Extra filename argument in direct file mode.");
 

libs/minisat/Solver.h

@@ -103,7 +103,7 @@ public:
     int     nFreeVars  ()      const;
     void    printStats ()      const;       // Print some current statistics to standard output.
 
-    // Resource contraints:
+    // Resource constraints:
     //
     void    setConfBudget(int64_t x);
     void    setPropBudget(int64_t x);
@@ -230,7 +230,7 @@ protected:
     double              learntsize_adjust_confl;
     int                 learntsize_adjust_cnt;
 
-    // Resource contraints:
+    // Resource constraints:
     //
     int64_t             conflict_budget;    // -1 means no budget.
     int64_t             propagation_budget; // -1 means no budget.

manual/CHAPTER_Prog/stubnets.cc

@@ -57,7 +57,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 		// we will record which bits of the (possibly multi-bit) wire are stub signals
 		std::set<int> stub_bits;
 
-		// get a signal description for this wire and split it into seperate bits
+		// get a signal description for this wire and split it into separate bits
 		RTLIL::SigSpec sig = sigmap(wire);
 
 		// for each bit (unless it is a constant):

manual/CHAPTER_Techmap.tex

@@ -32,7 +32,7 @@ the Yosys source tree.
 
 Additional features have been added to {\tt techmap} to allow for conditional
 mapping of cells (see {\tt help techmap} or Sec.~\ref{cmd:techmap}). This can
-for example be usefull if the target architecture supports hardware multipliers for
+for example be useful if the target architecture supports hardware multipliers for
 certain bit-widths but not for others.
 
 A usual synthesis flow would first use the {\tt techmap} pass to directly map

manual/CHAPTER_Verilog.tex

@@ -444,7 +444,7 @@ on the AST data structure:
 \begin{itemize}
 \item Inline all task and function calls.
 \item Evaluate all \lstinline[language=Verilog]{generate}-statements and unroll all \lstinline[language=Verilog]{for}-loops.
-\item Perform const folding where it is neccessary (e.g.~in the value part of {\tt AST\_PARAMETER}, {\tt AST\_LOCALPARAM},
+\item Perform const folding where it is necessary (e.g.~in the value part of {\tt AST\_PARAMETER}, {\tt AST\_LOCALPARAM},
 {\tt AST\_PARASET} and {\tt AST\_RANGE} nodes).
 \item Replace {\tt AST\_PRIMITIVE} nodes with appropriate {\tt AST\_ASSIGN} nodes.
 \item Replace dynamic bit ranges in the left-hand-side of assignments with {\tt AST\_CASE} nodes with {\tt AST\_COND} children
@@ -819,7 +819,7 @@ the \C{RTLIL::SyncRule}s that describe the output registers.
 %
 \item {\tt proc\_dff} \\
 This pass replaces the \C{RTLIL::SyncRule}s to d-type flip-flops (with
-asynchronous resets if neccessary).
+asynchronous resets if necessary).
 %
 \item {\tt proc\_clean} \\
 A final call to {\tt proc\_clean} removes the now empty \C{RTLIL::Process} objects.
@@ -827,7 +827,7 @@ A final call to {\tt proc\_clean} removes the now empty \C{RTLIL::Process} objec
 
 Performing these last processing steps in passes instead of in the Verilog frontend has two important benefits:
 
-First it improves the transparency of the process. Everything that happens in a seperate pass is easier to debug,
+First it improves the transparency of the process. Everything that happens in a separate pass is easier to debug,
 as the RTLIL data structures can be easily investigated before and after each of the steps.
 
 Second it improves flexibility. This scheme can easily be extended to support other types of storage-elements, such

manual/command-reference-manual.tex

@@ -85,10 +85,10 @@ This is just a shortcut for 'select -clear'.
 
 This is identical to 'opt_clean', but less verbose.
 
-When commands are seperated using the ';;' token, this command will be executed
+When commands are separated using the ';;' token, this command will be executed
 between the commands.
 
-When commands are seperated using the ';;;' token, this command will be executed
+When commands are separated using the ';;;' token, this command will be executed
 in -purge mode between the commands.
 \end{lstlisting}
 
@@ -419,7 +419,7 @@ commands.
     hierarchy [-check] [-top <module>]
     hierarchy -generate <cell-types> <port-decls>
 
-In parametric designs, a module might exists in serveral variations with
+In parametric designs, a module might exists in several variations with
 different parameter values. This pass looks at all modules in the current
 design an re-runs the language frontends for the parametric modules as
 needed.
@@ -881,7 +881,7 @@ The following options can be used to set up a sequential problem:
     -set-def-at <N> <signal>
     -set-any-undef-at <N> <signal>
     -set-all-undef-at <N> <signal>
-        add undef contraints in the given timestep.
+        add undef constraints in the given timestep.
 
     -set-init <signal> <value>
         set the initial value for the register driving the signal to the value
@@ -942,7 +942,7 @@ design.
 
     -all_cell_types
         Usually this command only considers internal non-memory cells. With
-        this option set, all cells are considered. For unkown cells all ports
+        this option set, all cells are considered. For unknown cells all ports
         are assumed to be bidirectional 'inout' ports.
 
     -set_attr <name> <value>
@@ -1089,7 +1089,7 @@ The following actions can be performed on the top sets on the stack:
         (i.e. select all cells connected to selected wires and select all
         wires connected to selected cells) The rules specify which cell
         ports to use for this. the syntax for a rule is a '-' for exclusion
-        and a '+' for inclusion, followed by an optional comma seperated
+        and a '+' for inclusion, followed by an optional comma separated
         list of cell types followed by an optional comma separated list of
         cell ports in square brackets. a rule can also be just a cell or wire
         name that limits the expansion (is included but does not go beyond).
@@ -1452,7 +1452,7 @@ Write the current design to an BLIF file.
     -false <cell-type> <out-port>
         use the specified cell types to drive nets that are constant 1 or 0
 
-The following options can be usefull when the generated file is not going to be
+The following options can be useful when the generated file is not going to be
 read by a BLIF parser but a custom tool. It is recommended to not name the output
 file *.blif when any of this options is used.
 

manual/manual.tex

@@ -144,7 +144,7 @@ Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
 with the help of HDL synthesis tools.
 
 In special cases such as synthesis for coarse-grain cell libraries or when
-testing new synthesis algorithms it might be neccessary to write a custom HDL
+testing new synthesis algorithms it might be necessary to write a custom HDL
 synthesis tool or add new features to an existing one. It this cases the
 availability of a Free and Open Source (FOSS) synthesis tool that can be used
 as basis for custom tools would be helpful.

passes/cmds/scc.cc

@@ -216,7 +216,7 @@ struct SccPass : public Pass {
 		log("\n");
 		log("    -all_cell_types\n");
 		log("        Usually this command only considers internal non-memory cells. With\n");
-		log("        this option set, all cells are considered. For unkown cells all ports\n");
+		log("        this option set, all cells are considered. For unknown cells all ports\n");
 		log("        are assumed to be bidirectional 'inout' ports.\n");
 		log("\n");
 		log("    -set_attr <name> <value>\n");

passes/cmds/select.cc

@@ -985,7 +985,7 @@ struct SelectPass : public Pass {
 		log("        (i.e. select all cells connected to selected wires and select all\n");
 		log("        wires connected to selected cells) The rules specify which cell\n");
 		log("        ports to use for this. the syntax for a rule is a '-' for exclusion\n");
-		log("        and a '+' for inclusion, followed by an optional comma seperated\n");
+		log("        and a '+' for inclusion, followed by an optional comma separated\n");
 		log("        list of cell types followed by an optional comma separated list of\n");
 		log("        cell ports in square brackets. a rule can also be just a cell or wire\n");
 		log("        name that limits the expansion (is included but does not go beyond).\n");
@@ -1089,7 +1089,7 @@ struct SelectPass : public Pass {
 				continue;
 			}
 			if (arg.size() > 0 && arg[0] == '-')
-				log_cmd_error("Unkown option %s.\n", arg.c_str());
+				log_cmd_error("Unknown option %s.\n", arg.c_str());
 			select_stmt(design, arg);
 			sel_str += " " + arg;
 		}

passes/cmds/splice.cc

@@ -251,12 +251,12 @@ struct SplicePass : public Pass {
 		log("\n");
 		log("    -sel_by_cell\n");
 		log("        only select the cell ports to rewire by the cell. if the selection\n");
-		log("        contains a cell, than all cell inputs are rewired, if neccessary.\n");
+		log("        contains a cell, than all cell inputs are rewired, if necessary.\n");
 		log("\n");
 		log("    -sel_by_wire\n");
 		log("        only select the cell ports to rewire by the wire. if the selection\n");
 		log("        contains a wire, than all cell ports driven by this wire are wired,\n");
-		log("        if neccessary.\n");
+		log("        if necessary.\n");
 		log("\n");
 		log("    -sel_any_bit\n");
 		log("        it is sufficient if the driver of any bit of a cell port is selected.\n");

passes/cmds/splitnets.cc

@@ -76,7 +76,7 @@ struct SplitnetsPass : public Pass {
 		log("    -format char1[char2[char3]]\n");
 		log("        the first char is inserted between the net name and the bit index, the\n");
 		log("        second char is appended to the netname. e.g. -format () creates net\n");
-		log("        names like 'mysignal(42)'. the 3rd character is the range seperation\n");
+		log("        names like 'mysignal(42)'. the 3rd character is the range separation\n");
 		log("        character when creating multi-bit wires. the default is '[]:'.\n");
 		log("\n");
 		log("    -ports\n");

passes/fsm/fsm_recode.cc

@@ -55,7 +55,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
 	log("Recoding FSM `%s' from module `%s' using `%s' encoding:\n", cell->name.c_str(), module->name.c_str(), encoding.c_str());
 
 	if (encoding != "none" && encoding != "one-hot" && encoding != "binary" && encoding != "auto") {
-		log("  unkown encoding `%s': using auto instead.\n", encoding.c_str());
+		log("  unknown encoding `%s': using auto instead.\n", encoding.c_str());
 		encoding = "auto";
 	}
 

passes/hierarchy/hierarchy.cc

@@ -216,7 +216,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 		int idx = it.second.first, num = it.second.second;
 
 		if (design->modules_.count(cell->type) == 0)
-			log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
+			log_error("Array cell `%s.%s' of unknown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
 
 		RTLIL::Module *mod = design->modules_[cell->type];
 
@@ -232,7 +232,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 					}
 			}
 			if (mod->wires_.count(portname) == 0)
-				log_error("Array cell `%s.%s' connects to unkown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
+				log_error("Array cell `%s.%s' connects to unknown port `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(conn.first));
 			int port_size = mod->wires_.at(portname)->width;
 			if (conn_size == port_size)
 				continue;
@@ -294,7 +294,7 @@ struct HierarchyPass : public Pass {
 		log("    hierarchy [-check] [-top <module>]\n");
 		log("    hierarchy -generate <cell-types> <port-decls>\n");
 		log("\n");
-		log("In parametric designs, a module might exists in serveral variations with\n");
+		log("In parametric designs, a module might exists in several variations with\n");
 		log("different parameter values. This pass looks at all modules in the current\n");
 		log("design an re-runs the language frontends for the parametric modules as\n");
 		log("needed.\n");
@@ -309,7 +309,7 @@ struct HierarchyPass : public Pass {
 		log("\n");
 		log("    -libdir <directory>\n");
 		log("        search for files named <module_name>.v in the specified directory\n");
-		log("        for unkown modules and automatically run read_verilog for each\n");
+		log("        for unknown modules and automatically run read_verilog for each\n");
 		log("        unknown module.\n");
 		log("\n");
 		log("    -keep_positionals\n");

passes/memory/memory_share.cc

@@ -720,7 +720,7 @@ struct MemorySharePass : public Pass {
 		log("    address, then this feedback path is converted to a write port with\n");
 		log("    byte/part enable signals.\n");
 		log("\n");
-		log("  - When multiple write ports access the same adress then this is converted\n");
+		log("  - When multiple write ports access the same address then this is converted\n");
 		log("    to a single write port with a more complex data and/or enable logic path.\n");
 		log("\n");
 		log("  - When multiple write ports are never accessed at the same time (a SAT\n");

passes/opt/opt_clean.cc

@@ -367,10 +367,10 @@ struct CleanPass : public Pass {
 		log("\n");
 		log("This is identical to 'opt_clean', but less verbose.\n");
 		log("\n");
-		log("When commands are seperated using the ';;' token, this command will be executed\n");
+		log("When commands are separated using the ';;' token, this command will be executed\n");
 		log("between the commands.\n");
 		log("\n");
-		log("When commands are seperated using the ';;;' token, this command will be executed\n");
+		log("When commands are separated using the ';;;' token, this command will be executed\n");
 		log("in -purge mode between the commands.\n");
 		log("\n");
 	}

passes/sat/sat.cc

@@ -874,7 +874,7 @@ struct SatPass : public Pass {
 		log("    -set-def-at <N> <signal>\n");
 		log("    -set-any-undef-at <N> <signal>\n");
 		log("    -set-all-undef-at <N> <signal>\n");
-		log("        add undef contraints in the given timestep.\n");
+		log("        add undef constraints in the given timestep.\n");
 		log("\n");
 		log("    -set-init <signal> <value>\n");
 		log("        set the initial value for the register driving the signal to the value\n");