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Fixes

This commit is contained in:
Eddie Hung 2020-01-06 11:53:48 -08:00
parent d152fe961f
commit 64ace4b0dc
1 changed files with 3 additions and 0 deletions
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3
passes/techmap/abc9.cc
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@ -411,6 +411,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
if (mapped_mod == NULL) if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `$__abc9__'.\n"); log_error("ABC output file does not contain a module `$__abc9__'.\n");
for (auto w : mapped_mod->wires())
module->addWire(remap_name(w->name), GetSize(w));
dict<IdString, bool> abc9_box; dict<IdString, bool> abc9_box;
vector<RTLIL::Cell*> boxes; vector<RTLIL::Cell*> boxes;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {