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removed unused bib 

removed unused bibitems from the appnote verilog to btor
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Ahmed Irfan 2014-11-03 16:24:26 +01:00
parent 3dd316bdc7
commit 6460d094e5
1 changed files with 12 additions and 12 deletions
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24
manual/APPNOTE_012_Verilog_to_BTOR.tex
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@ -397,21 +397,21 @@ verification benchmarks with or without memories from Verilog design.
Clifford Wolf. The Yosys Open SYnthesis Suite. \\ Clifford Wolf. The Yosys Open SYnthesis Suite. \\
\url{http://www.clifford.at/yosys/} \url{http://www.clifford.at/yosys/}
\bibitem{bigsim} %\bibitem{bigsim}
yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\ %yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\
\url{https://github.com/cliffordwolf/yosys-bigsim} %\url{https://github.com/cliffordwolf/yosys-bigsim}
\bibitem{navre} %\bibitem{navre}
Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\ %Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\
\url{http://opencores.org/project,navre} %\url{http://opencores.org/project,navre}
\bibitem{amber} %\bibitem{amber}
Conor Santifort. Amber ARM-compatible core. \\ %Conor Santifort. Amber ARM-compatible core. \\
\url{http://opencores.org/project,amber} %\url{http://opencores.org/project,amber}
\bibitem{ABC} %\bibitem{ABC}
Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. \\ %Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. \\
\url{http://www.eecs.berkeley.edu/~alanmi/abc/} %\url{http://www.eecs.berkeley.edu/~alanmi/abc/}
\bibitem{boolector} \bibitem{boolector}
Robert Brummayer and Armin Biere, Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays\\ Robert Brummayer and Armin Biere, Boolector: An Efficient SMT Solver for Bit-Vectors and Arrays\\