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Bugfix in opt_expr handling of a<0 and a>=0 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-12-06 07:29:21 +01:00
parent 910d94b212
commit 643f858acf
1 changed files with 1 additions and 1 deletions
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2
passes/opt/opt_expr.cc
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@ -1406,7 +1406,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false) if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
{ {
if (sigConst.is_fully_zero()) { if (sigConst.is_fully_zero()) {
RTLIL::SigSpec a_prime(RTLIL::State::S0, 1); RTLIL::SigSpec a_prime(RTLIL::State::S0, GetSize(cell->getPort("\\Y")));
if (is_lt) { if (is_lt) {
log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n", log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
log_id(cell->type), log_id(cell)); log_id(cell->type), log_id(cell));