mirror of https://github.com/YosysHQ/yosys.git
Copy not move parameters/attributes
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@ -599,11 +599,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
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RTLIL::Cell *existing_cell = module->cell(c->name);
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RTLIL::Cell *existing_cell = module->cell(c->name);
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if (existing_cell) {
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if (existing_cell) {
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cell->parameters = std::move(existing_cell->parameters);
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cell->parameters = existing_cell->parameters;
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cell->attributes = std::move(existing_cell->attributes);
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cell->attributes = existing_cell->attributes;
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}
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}
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else {
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else {
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cell->parameters = std::move(c->parameters);
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cell->parameters = c->parameters;
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cell->attributes = c->attributes;
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}
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}
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for (auto &conn : c->connections()) {
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for (auto &conn : c->connections()) {
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RTLIL::SigSpec newsig;
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RTLIL::SigSpec newsig;
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