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Rename

This commit is contained in:
Eddie Hung 2019-09-09 16:45:38 -07:00
parent 1df9c5d277
commit 6348f9512c
1 changed files with 27 additions and 27 deletions
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54
passes/pmgen/xilinx_dsp.pmg
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@ -10,8 +10,8 @@ state <int> ffPoffset
state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux
// subpattern // subpattern
state <SigSpec> dffQ state <SigSpec> argQ
state <bool> dffenpol_ state <bool> ffenpol
udata <SigSpec> dffD udata <SigSpec> dffD
udata <SigBit> dffclock udata <SigBit> dffclock
udata <Cell*> dff dffmux udata <Cell*> dff dffmux
@ -51,9 +51,9 @@ code unextend sigA sigB sigC sigD sigM
// reject; // reject;
endcode endcode
code dffQ ffAD ffADmux ffADenpol sigA clock code argQ ffAD ffADmux ffADenpol sigA clock
if (param(dsp, \ADREG).as_int() == 0) { if (param(dsp, \ADREG).as_int() == 0) {
dffQ = sigA; argQ = sigA;
subpattern(in_dffe); subpattern(in_dffe);
if (dff) { if (dff) {
ffAD = dff; ffAD = dff;
@ -97,12 +97,12 @@ code sigA sigD
} }
endcode endcode
code dffQ ffA ffAmux ffAenpol sigA clock ffAD ffADmux ffADenpol code argQ ffA ffAmux ffAenpol sigA clock ffAD ffADmux ffADenpol
// Only search for ffA if there was a pre-adder // Only search for ffA if there was a pre-adder
// (otherwise ffA would have been matched as ffAD) // (otherwise ffA would have been matched as ffAD)
if (preAdd) { if (preAdd) {
if (param(dsp, \AREG).as_int() == 0) { if (param(dsp, \AREG).as_int() == 0) {
dffQ = sigA; argQ = sigA;
subpattern(in_dffe); subpattern(in_dffe);
if (dff) { if (dff) {
ffA = dff; ffA = dff;
@ -125,9 +125,9 @@ code dffQ ffA ffAmux ffAenpol sigA clock ffAD ffADmux ffADenpol
} }
endcode endcode
code dffQ ffB ffBmux ffBenpol sigB clock code argQ ffB ffBmux ffBenpol sigB clock
if (param(dsp, \BREG).as_int() == 0) { if (param(dsp, \BREG).as_int() == 0) {
dffQ = sigB; argQ = sigB;
subpattern(in_dffe); subpattern(in_dffe);
if (dff) { if (dff) {
ffB = dff; ffB = dff;
@ -141,9 +141,9 @@ code dffQ ffB ffBmux ffBenpol sigB clock
} }
endcode endcode
code dffQ ffD ffDmux ffDenpol sigD clock code argQ ffD ffDmux ffDenpol sigD clock
if (param(dsp, \DREG).as_int() == 0) { if (param(dsp, \DREG).as_int() == 0) {
dffQ = sigD; argQ = sigD;
subpattern(in_dffe); subpattern(in_dffe);
if (dff) { if (dff) {
ffD = dff; ffD = dff;
@ -367,9 +367,9 @@ code sigC
sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A); sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
endcode endcode
code dffQ ffC ffCmux ffCenpol sigC clock code argQ ffC ffCmux ffCenpol sigC clock
if (param(dsp, \CREG).as_int() == 0) { if (param(dsp, \CREG).as_int() == 0) {
dffQ = sigC; argQ = sigC;
subpattern(in_dffe); subpattern(in_dffe);
if (dff) { if (dff) {
ffC = dff; ffC = dff;
@ -388,22 +388,22 @@ code
endcode endcode
subpattern in_dffe subpattern in_dffe
arg dffQ clock dffenpol_ arg argQ clock ffenpol
match ff match ff
select ff->type.in($dff) select ff->type.in($dff)
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
select param(ff, \CLK_POLARITY).as_bool() select param(ff, \CLK_POLARITY).as_bool()
filter GetSize(port(ff, \Q)) >= GetSize(dffQ) filter GetSize(port(ff, \Q)) >= GetSize(argQ)
slice offset GetSize(port(ff, \Q)) slice offset GetSize(port(ff, \Q))
filter offset+GetSize(dffQ) <= GetSize(port(ff, \Q)) filter offset+GetSize(argQ) <= GetSize(port(ff, \Q))
filter port(ff, \Q).extract(offset, GetSize(dffQ)) == dffQ filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
semioptional semioptional
endmatch endmatch
code dffQ code argQ
if (ff) { if (ff) {
for (auto b : dffQ) for (auto b : argQ)
if (b.wire->get_bool_attribute(\keep)) if (b.wire->get_bool_attribute(\keep))
reject; reject;
@ -414,22 +414,22 @@ code dffQ
dffclock = port(ff, \CLK); dffclock = port(ff, \CLK);
dff = ff; dff = ff;
dffD = dffQ; dffD = argQ;
dffD.replace(port(ff, \Q), port(ff, \D)); dffD.replace(port(ff, \Q), port(ff, \D));
// Only search for ffmux if ff.Q has at // Only search for ffmux if ff.Q has at
// least 3 users (ff, dsp, ffmux) and // least 3 users (ff, dsp, ffmux) and
// its ff.D only has two (ff, ffmux) // its ff.D only has two (ff, ffmux)
if (!(nusers(dffQ) >= 3 && nusers(dffD) == 2)) if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
dffQ = SigSpec(); argQ = SigSpec();
} }
else { else {
dff = nullptr; dff = nullptr;
dffQ = SigSpec(); argQ = SigSpec();
} }
endcode endcode
match ffmux match ffmux
if !dffQ.empty() if !argQ.empty()
select ffmux->type.in($mux) select ffmux->type.in($mux)
index <SigSpec> port(ffmux, \Y) === port(ff, \D) index <SigSpec> port(ffmux, \Y) === port(ff, \D)
filter GetSize(port(ffmux, \Y)) >= GetSize(dffD) filter GetSize(port(ffmux, \Y)) >= GetSize(dffD)
@ -437,17 +437,17 @@ match ffmux
filter offset+GetSize(dffD) <= GetSize(port(ffmux, \Y)) filter offset+GetSize(dffD) <= GetSize(port(ffmux, \Y))
filter port(ffmux, \Y).extract(offset, GetSize(dffD)) == dffD filter port(ffmux, \Y).extract(offset, GetSize(dffD)) == dffD
choice <IdString> AB {\A, \B} choice <IdString> AB {\A, \B}
filter offset+GetSize(dffQ) <= GetSize(port(ffmux, \Y)) filter offset+GetSize(argQ) <= GetSize(port(ffmux, \Y))
filter port(ffmux, AB).extract(offset, GetSize(dffQ)) == dffQ filter port(ffmux, AB).extract(offset, GetSize(argQ)) == argQ
define <bool> pol (AB == \A) define <bool> pol (AB == \A)
set dffenpol_ pol set ffenpol pol
semioptional semioptional
endmatch endmatch
code code
if (ffmux) { if (ffmux) {
dffmux = ffmux; dffmux = ffmux;
dffenpol = dffenpol_; dffenpol = ffenpol;
dffD = port(ffmux, dffenpol ? \B : \A); dffD = port(ffmux, dffenpol ? \B : \A);
} }
else else