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Renamed temp module generated by "abc" pass from "logic" to "netlist"

This commit is contained in:
Clifford Wolf 2013-11-19 01:03:57 +01:00
parent c5e26f839c
commit 63285b300c
2 changed files with 6 additions and 6 deletions
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10
passes/abc/abc.cc
View File

@ -340,7 +340,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
if (!cleanup) if (!cleanup)
tempdir_name[0] = tempdir_name[4] = '_'; tempdir_name[0] = tempdir_name[4] = '_';
char *p = mkdtemp(tempdir_name); char *p = mkdtemp(tempdir_name);
log_header("Extracting gate logic of module `%s' to `%s/input.v'..\n", module->name.c_str(), tempdir_name); log_header("Extracting gate netlist of module `%s' to `%s/input.v'..\n", module->name.c_str(), tempdir_name);
if (p == NULL) if (p == NULL)
log_error("For some reason mkdtemp() failed!\n"); log_error("For some reason mkdtemp() failed!\n");
@ -369,7 +369,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
log_error("Opening %s for writing failed: %s\n", p, strerror(errno)); log_error("Opening %s for writing failed: %s\n", p, strerror(errno));
free(p); free(p);
fprintf(f, "module logic ("); fprintf(f, "module netlist (");
bool first = true; bool first = true;
for (auto &si : signal_list) { for (auto &si : signal_list) {
if (!si.is_port) if (!si.is_port)
@ -419,7 +419,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
fprintf(f, "endmodule\n"); fprintf(f, "endmodule\n");
fclose(f); fclose(f);
log("Extracted %d gates and %zd wires to a logic network with %d inputs and %d outputs.\n", log("Extracted %d gates and %zd wires to a netlist network with %d inputs and %d outputs.\n",
count_gates, signal_list.size(), count_input, count_output); count_gates, signal_list.size(), count_input, count_output);
log_push(); log_push();
@ -510,9 +510,9 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
free(p); free(p);
log_header("Re-integrating ABC results.\n"); log_header("Re-integrating ABC results.\n");
RTLIL::Module *mapped_mod = mapped_design->modules["\\logic"]; RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"];
if (mapped_mod == NULL) if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `logic'.\n"); log_error("ABC output file does not contain a module `netlist'.\n");
for (auto &it : mapped_mod->wires) { for (auto &it : mapped_mod->wires) {
RTLIL::Wire *w = it.second; RTLIL::Wire *w = it.second;
RTLIL::Wire *wire = new RTLIL::Wire; RTLIL::Wire *wire = new RTLIL::Wire;

2
passes/abc/blifparse.cc
View File

@ -53,7 +53,7 @@ RTLIL::Design *abc_parse_blif(FILE *f)
RTLIL::State lut_default_state = RTLIL::State::Sx; RTLIL::State lut_default_state = RTLIL::State::Sx;
int port_count = 0; int port_count = 0;
module->name = "\\logic"; module->name = "\\netlist";
design->modules[module->name] = module; design->modules[module->name] = module;
char buffer[4096]; char buffer[4096];