mirror of https://github.com/YosysHQ/yosys.git
Added $alu support to test_cell
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@ -95,6 +95,27 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type,
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cell->setPort("\\Y", wire);
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cell->setPort("\\Y", wire);
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}
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}
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if (cell_type == "$alu")
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{
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wire = module->addWire("\\CI");
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wire->port_input = true;
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cell->setPort("\\CI", wire);
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wire = module->addWire("\\BI");
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wire->port_input = true;
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cell->setPort("\\BI", wire);
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wire = module->addWire("\\X");
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wire->width = SIZE(cell->getPort("\\Y"));
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wire->port_output = true;
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cell->setPort("\\X", wire);
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wire = module->addWire("\\CO");
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wire->width = SIZE(cell->getPort("\\Y"));
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wire->port_output = true;
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cell->setPort("\\CO", wire);
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}
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module->fixup_ports();
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module->fixup_ports();
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cell->fixup_parameters();
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cell->fixup_parameters();
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cell->check();
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cell->check();
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@ -317,7 +338,7 @@ struct TestCellPass : public Pass {
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// cell_types["$assert"] = "A";
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// cell_types["$assert"] = "A";
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cell_types["$lut"] = "*";
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cell_types["$lut"] = "*";
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// cell_types["$alu"] = "*";
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cell_types["$alu"] = "ABSY";
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for (; argidx < SIZE(args); argidx++)
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for (; argidx < SIZE(args); argidx++)
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{
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{
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