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abc9 to cope with indexed wires when creating $lut from $_NOT_

This commit is contained in:
Eddie Hung 2019-02-19 16:06:03 -08:00
parent ef1a1402bc
commit 62e5ff9ba8
1 changed files with 6 additions and 1 deletions
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7
passes/techmap/abc9.cc
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@ -597,7 +597,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// Otherwise, clone the driving LUT to guarantee that we // Otherwise, clone the driving LUT to guarantee that we
// won't increase the max logic depth // won't increase the max logic depth
// (TODO: Optimise by not cloning unless will increase depth) // (TODO: Optimise by not cloning unless will increase depth)
RTLIL::Cell* driver = mapped_mod->cell(stringf("%s_lut", a_bit.wire->name.c_str())); RTLIL::IdString driver_name;
if (GetSize(a_bit.wire) == 1)
driver_name = stringf("%s_lut", a_bit.wire->name.c_str());
else
driver_name = stringf("%s[%d]_lut", a_bit.wire->name.c_str(), a_bit.offset);
RTLIL::Cell* driver = mapped_mod->cell(driver_name);
log_assert(driver); log_assert(driver);
auto driver_a = driver->getPort("\\A").chunks(); auto driver_a = driver->getPort("\\A").chunks();
for (auto &chunk : driver_a) for (auto &chunk : driver_a)